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| document no. u16228ej2v0ud00 (2nd edition) date published november 2003 n cp(k) printed in japan 2002 pd780131 pd780132 pd780132(a) pd780132(a1) pd780132(a2) pd780133 pd780133(a) pd780133(a1) pd780133(a2) pd780134 pd780134(a) pd780134(a1) pd780134(a2) pd780136 pd780136(a) pd780136(a1) pd780136(a2) pd780138 pd780138(a) pd780138(a1) pd780138(a2) pd78f0134 pd78f0134(a) pd78f0134(a1) pd78f0138 pd78f0138(a) pd78f0138(a1) 78k0/ke1 8-bit single-chip microcontrollers user?s manual
user?s manual u16228ej2v0ud 2 [memo] user?s manual u16228ej2v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom is a trademark of nec electronics corporation. windows and windows nt are either registered trademarks or trademar ks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron. user?s manual u16228ej2v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of may, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 user?s manual u16228ej2v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 succursale fran?aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user?s manual u16228ej2v0ud 6 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0/ke1 and design and dev elop application systems and programs for these devices. the target products are as follows. 78k0/ke1: pd780131, 780132, 780133, 780134, 780136, 780138, 78f0134, 78f0138, 780131(a), 780132(a), 780133(a), 780134(a), 780136(a), 780138(a), 78f0134(a), 78f0138(a) , 780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1 ), 780138(a1), 78f0134(a1), 78f0138(a1), 780131(a2), 780132(a2 ), 780133(a2), 780134(a2), 780136(a2), and 780138(a2) purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/ke1 manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). 78k0/ke1 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction user?s manual u16228ej2v0ud 7 how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? ? ? ? ? ? ? ? ? ? ? ? ? user?s manual u16228ej2v0ud 8 related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/ke1 user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u14445e language u14446e ra78k0 assembler package structured assembly language u11789e operation u14297e cc78k0 c compiler language u14298e operation (windows tm based) u15373e sm78k series system simulator ver. 2.30 or later external part user open interface specifications u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e fundamentals u11537e rx78k0 real-time os installation u11536e project manager ver. 3.12 or later (windows based) u14610e documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0k1-et in-circuit emulator to be prepared ie-780148-ns-em1 emulation board to be prepared documents related to fl ash memory programming document name document no. pg-fp3 flash memory programmer user?s manual u13502e pg-fp4 flash memory programmer user?s manual u15260e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u16228ej2v0ud 9 other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u16228ej2v0ud 10 contents chapter 1 outline ........................................................................................................... ................. 18 1.1 features ................................................................................................................... ................... 18 1.2 applications............................................................................................................... ................. 19 1.3 ordering information ....................................................................................................... .......... 20 1.4 pin configuration (top view)............................................................................................... ..... 27 1.5 k1 family lineup........................................................................................................... ............. 29 1.5.1 78k0/kx1 pr oduct lineup.................................................................................................. .............. 29 1.5.2 v850es/kx1 product li neup ................................................................................................ ........... 31 1.6 block diagram .............................................................................................................. .............. 33 1.7 outline of functions ....................................................................................................... ........... 34 chapter 2 pin functions .................................................................................................... ........... 36 2.1 pin function list .......................................................................................................... .............. 36 2.2 description of pin functions ............................................................................................... ..... 40 2.2.1 p00 to p06 (por t 0) ...................................................................................................... .................. 40 2.2.2 p10 to p17 (por t 1) ...................................................................................................... .................. 41 2.2.3 p20 to p27 (por t 2) ...................................................................................................... .................. 41 2.2.4 p30 to p33 (por t 3) ...................................................................................................... .................. 42 2.2.5 p40 to p43 (por t 4) ...................................................................................................... .................. 42 2.2.6 p50 to p53 (por t 5) ...................................................................................................... .................. 42 2.2.7 p60 to p63 (por t 6) ...................................................................................................... .................. 42 2.2.8 p70 to p77 (por t 7) ...................................................................................................... .................. 42 2.2.9 p120 (port 12)........................................................................................................... ..................... 43 2.2.10 p130 (port 13).......................................................................................................... ...................... 43 2.2.11 p140 and p141 ( port 14) ................................................................................................. .............. 43 2.2.12 av ref .............................................................................................................................. .............. 43 2.2.13 av ss .............................................................................................................................. ................ 43 2.2.14 reset................................................................................................................... ........................ 44 2.2.15 regc .................................................................................................................... ........................ 44 2.2.16 x1 and x2 ............................................................................................................... ....................... 44 2.2.17 xt 1 and xt 2............................................................................................................. ..................... 44 2.2.18 v dd and ev dd .............................................................................................................................. .. 44 2.2.19 v ss and ev ss .............................................................................................................................. .. 44 2.2.20 v pp (flash memory versions only) .................................................................................................. 44 2.2.21 ic (mask rom versions only) ............................................................................................. ........... 44 2.3 pin i/o circuits and recommende d connection of unused pins......................................... 45 chapter 3 cpu architecture ................................................................................................. ..... 49 3.1 memory space ............................................................................................................... ............. 49 3.1.1 internal progr am memory space ............................................................................................ ........ 58 3.1.2 internal data memory space ............................................................................................... ........... 59 3.1.3 special function register (s fr) area..................................................................................... ......... 59 3.1.4 data memo ry addre ssing................................................................................................... ............ 60 user?s manual u16228ej2v0ud 11 3.2 processor registers ........................................................................................................ .......... 68 3.2.1 control registers ........................................................................................................ .....................68 3.2.2 general-purpo se regi sters ................................................................................................ ..............72 3.2.3 special functi on register s (sfrs)........................................................................................ .........73 3.3 instruction address addressing ................................... .......................................................... .78 3.3.1 relative addre ssing ...................................................................................................... ..................78 3.3.2 immediat e addre ssing ..................................................................................................... ...............79 3.3.3 table indi rect addr essing ................................................................................................ ...............80 3.3.4 register addre ssing ...................................................................................................... ..................80 3.4 operand address addressing ............. .................................................................................... .81 3.4.1 impli ed addres sing ....................................................................................................... ..................81 3.4.2 register addre ssing ...................................................................................................... ..................82 3.4.3 direct addre ssing........................................................................................................ ....................83 3.4.4 short dire ct addressing.................................................................................................. .................84 3.4.5 special function r egister (sfr ) addre ssing ............................................................................... .....85 3.4.6 register i ndirect addr essing ............................................................................................. ..............86 3.4.7 based addres sing......................................................................................................... ..................87 3.4.8 based index ed addres sing ................................................................................................. ............88 3.4.9 stack addressi ng ......................................................................................................... ...................89 chapter 4 port functions ................................................................................................... ........ 90 4.1 port functions............................................................................................................. ............... 90 4.2 port configuratio n ......................................................................................................... ............ 92 4.2.1 port 0................................................................................................................... ...........................93 4.2.2 port 1................................................................................................................... ...........................97 4.2.3 port 2................................................................................................................... .........................102 4.2.4 port 3................................................................................................................... .........................103 4.2.5 port 4................................................................................................................... .........................105 4.2.6 port 5................................................................................................................... .........................106 4.2.7 port 6................................................................................................................... .........................107 4.2.8 port 7................................................................................................................... .........................108 4.2.9 po rt 12.................................................................................................................. ........................109 4.2.10 po rt 13................................................................................................................. .........................110 4.2.11 po rt 14................................................................................................................. .........................111 4.3 registers controlling po rt function...................................................................................... 11 2 4.4 port function operations.......................................... ......................................................... ..... 116 4.4.1 writing to i/o port ...................................................................................................... ...................116 4.4.2 reading from i/o port .................................................................................................... ...............116 4.4.3 operatio ns on i/o port ................................................................................................... ...............116 chapter 5 clock generator .................................................................................................. .. 117 5.1 functions of clock generator ... ............................................................................................ . 117 5.2 configuration of clock generato r.......................................................................................... 1 17 5.3 registers controlling clock generator ..................... ............................................................ 119 5.4 system clock oscillator.................................................................................................... ...... 126 user?s manual u16228ej2v0ud 12 5.4.1 x1 o scillat or ............................................................................................................ ......................126 5.4.2 subsystem cl ock osc illator............................................................................................... .............126 5.4.3 when subsystem clock is not us ed......................................................................................... ......129 5.4.4 ring-osc oscilla tor ...................................................................................................... ................129 5.4.5 pre scaler................................................................................................................ .......................129 5.5 clock generator operation ............................................. ..................................................... ... 130 5.6 time required to switch between ring-osc clo ck and x1 input clock........................... 137 5.7 time required for cpu clock switchover................... .......................................................... 138 5.8 clock switching flowchart and re gister setting ................................................................. 139 5.8.1 switching from ring-osc clock to x1 input cl ock.........................................................................1 39 5.8.2 switching from x1 input clock to ri ng-osc cl ock.........................................................................1 40 5.8.3 switching from x1 input clock to sub system cl ock........................................................................1 41 5.8.4 switching from subsystem clock to x1 input cl ock........................................................................1 42 5.8.5 register settings ........................................................................................................ ...................143 chapter 6 16-bit timer/event counters 00 and 01......................................................... 144 6.1 functions of 16-bit timer/ event counters 00 and 01............. .............................................. 144 6.2 configuration of 16-bit timer/ event counters 00 and 01 ............... ..................................... 145 6.3 registers controlling 16-bit timer/event counters 00 and 01 ...... ..................................... 150 6.4 operation of 16-bit timer/event counters 00 and 01........................................................... 160 6.4.1 interval ti mer operation ................................................................................................. ................160 6.4.2 ppg output operations .................................................................................................... .............163 6.4.3 pulse width me asurement operati ons ....................................................................................... ....166 6.4.4 external event counter o peration ......................................................................................... .........174 6.4.5 square-wave output oper ation............................................................................................. .........177 6.4.6 one-shot puls e output op eration.......................................................................................... .........179 6.5 cautions for 16-bit timer/event counters 00 and 01 ........................................................... 184 chapter 7 8-bit timer/event counters 50 and 51........................................................... 187 7.1 functions of 8-bit time r/event counters 50 and 51............... .............................................. 187 7.2 configuration of 8-bit timer/ event counters 50 and 51 ............. ......................................... 189 7.3 registers controlling 8-bit timer/event counters 50 and 51 ............................................. 191 7.4 operations of 8-bit timer/event counters 50 and 51........................................................... 196 7.4.1 operation as interval timer.............................................................................................. ..............196 7.4.2 operation as ex ternal event count er...................................................................................... .......198 7.4.3 square-wave output oper ation............................................................................................. .........199 7.4.4 pwm output operat ion ..................................................................................................... .............200 7.5 cautions for 8-bit timer/event counters 50 and 51 ............................................................. 204 chapter 8 8-bit timers h0 and h1 ........................................................................................ .. 205 8.1 functions of 8-bit timers h0 and h1 ........................... .......................................................... 205 8.2 configuration of 8-bit timers h0 and h1................. .............................................................. 205 8.3 registers controlling 8-bit timers h0 and h1 ........ .............................................................. 209 8.4 operation of 8-bit timers h0 and h1 ....................... .............................................................. 214 8.4.1 operation as interval timer/square- wave ou tput ........................................................................... 214 user?s manual u16228ej2v0ud 13 8.4.2 operation as pwm output mode ............................................................................................. .....217 8.4.3 carrier generator mode oper ation (8-bit ti mer h1 only) ................................................................223 chapter 9 watch timer ...................................................................................................... ......... 230 9.1 functions of watch timer......................................... .......................................................... .... 230 9.2 configuration of watch timer .................................. ............................................................. . 232 9.3 register controlling watch timer.......................................................................................... 2 32 9.4 watch timer operations ..................................................................................................... .... 234 9.4.1 watch time r operation .................................................................................................... ..............234 9.4.2 interval ti mer operation................................................................................................. ................235 9.5 cautions for watch timer ................................................................................................... .... 236 chapter 10 watchdog timer .................................................................................................. ... 237 10.1 functions of watchdog timer ............................................................................................... . 237 10.2 configuration of watchdog timer.............................. ............................................................ 2 39 10.3 registers controlling watchdog time r ................................................................................. 240 10.4 operation of watchdog timer ............................................................................................... . 242 10.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by a mask option ...242 10.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask opt ion .................................................................................................................... ..............243 10.4.3 watchdog timer operation in stop mode (wh en ?ring-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .......244 10.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .......246 chapter 11 clock output/buzzer output controller............................................... 247 11.1 functions of clock outp ut/buzzer output controll er.......................................................... 247 11.2 configuration of clock output/b uzzer output controller ................................................... 248 11.3 register controlling clock out put/buzzer output controller............................................. 248 11.4 clock output/buzzer output cont roller operations ............................................................ 250 11.4.1 clock output operation.................................................................................................. ................250 11.4.2 operation as buzzer output .............................................................................................. ............250 chapter 12 a/d converter ................................................................................................... ...... 251 12.1 functions of a/d conver ter ................................................................................................ .... 251 12.2 configuration of a/d converter................................ ............................................................ .. 252 12.3 registers used in a/d converter ........................................................................................... 254 12.4 a/d converter operations.................................................................................................. ..... 259 12.4.1 basic operations of a/d c onverter ....................................................................................... .........259 12.4.2 input volt age and conversi on results .................................................................................... ........261 12.4.3 a/d converte r operati on mode............................................................................................ ..........262 12.5 how to read a/d converter char acteristics table .............................................................. 265 12.6 cautions for a/d converter................................................................................................ ..... 267 chapter 13 serial interface uart0 ...................................................................................... 272 13.1 functions of serial interface uart0 ......................... ............................................................ 27 2 user?s manual u16228ej2v0ud 14 13.2 configuration of serial interf ace uart0 ............................................................................... 273 13.3 registers controlling serial in terface uart0....................................................................... 276 13.4 operation of serial interface uart0 ............................ .......................................................... 2 81 13.4.1 operatio n stop mode ..................................................................................................... ...............281 13.4.2 asynchronous serial interface (u art) mode............................................................................... .282 13.4.3 dedicated baud rate generator ........................................................................................... ..........288 chapter 14 serial interface uart6 ...................................................................................... 293 14.1 functions of serial interface uart6.............................. ........................................................ 2 93 14.2 configuration of serial interf ace uart6 ............................................................................... 297 14.3 registers controlling serial in terface uart6....................................................................... 300 14.4 operation of serial interface uart6 ............................ .......................................................... 3 08 14.4.1 operatio n stop mode ..................................................................................................... ...............308 14.4.2 asynchronous serial interface (u art) mode............................................................................... .309 14.4.3 dedicated baud rate generator ........................................................................................... ..........324 chapter 15 serial interfaces csi10 and csi11 ................................................................ 331 15.1 functions of serial interfaces csi 10 and csi11 ................................................................... 331 15.2 configuration of serial interfaces csi10 and csi1 1............................................................. 332 15.3 registers controlling serial interfaces csi10 a nd csi11 .................................................... 334 15.4 operation of serial interfaces cs i10 and csi11 ................................................................... 340 15.4.1 operatio n stop mode ..................................................................................................... ...............340 15.4.2 3-wire se rial i/o mode.................................................................................................. .................341 chapter 16 multiplier/divider ............................................................................................... .... 351 16.1 functions of multiplier/div ider ........................................................................................... .... 351 16.2 configuration of multiplier/di vider ....................................................................................... .. 351 16.3 register controlling multiplier/ divider .................................................................................. 3 55 16.4 operations of multiplier/divi der.......................................................................................... .... 356 16.4.1 multiplicati on operation ................................................................................................ .................356 16.4.2 division operat ion ...................................................................................................... ...................358 chapter 17 interrupt functions ............................................................................................ 3 60 17.1 interrupt function types.................................................................................................. ....... 360 17.2 interrupt sources and configuration ........................... .......................................................... 36 0 17.3 registers controlling interrupt functions ............................................................................ 364 17.4 interrupt servicing operati ons ............................................................................................ ... 371 17.4.1 maskable interrupt acknowl edgement ...................................................................................... ....371 17.4.2 software interrupt request ack nowledgement.............................................................................. .373 17.4.3 multiple inte rrupt servicing ............................................................................................ ................374 17.4.4 interrupt request hold.................................................................................................. ..................377 chapter 18 key interrupt function ..................................................................................... 378 18.1 functions of key interrupt .............................................. .................................................. ...... 378 18.2 configuration of key interrupt............................................................................................ .... 378 18.3 register controlling key interrupt ............................... ......................................................... . 379 user?s manual u16228ej2v0ud 15 chapter 19 standby function ................................................................................................ .. 380 19.1 standby function and configuratio n .................................................................................... 380 19.1.1 standby functi on........................................................................................................ ...................380 19.1.2 registers contro lling standby function .................................................................................. ........382 19.2 standby function operation..................................... ........................................................... ... 384 19.2.1 halt mode ............................................................................................................... ...................384 19.2.2 stop mode............................................................................................................... ...................389 chapter 20 reset function .................................................................................................. ..... 393 20.1 register for confirming reset source .................................................................................. 400 chapter 21 clock monitor ................................................................................................... ..... 401 21.1 functions of clock monitor ................................................................................................ .... 401 21.2 configuration of clock monitor ............................................................................................ .. 401 21.3 registers controlling clock monito r ..................................................................................... 40 2 21.4 operation of clock monitor................................................................................................ ..... 403 chapter 22 power-on-clear circuit ..................................................................................... 408 22.1 functions of power-on-cl ear circuit ..................................................................................... 40 8 22.2 configuration of power-on-clear circuit............................................................................... 409 22.3 operation of power-on-clear circuit ....................... .............................................................. 40 9 22.4 cautions for power-on-clear circ uit...................................................................................... 4 10 chapter 23 low-voltage detector ....................................................................................... 412 23.1 functions of low-voltage detector ....................................................................................... 41 2 23.2 configuration of low-voltage de tector................................................................................. 412 23.3 registers controlling low-voltage detector ........................................................................ 413 23.4 operation of low-voltage detector ........................... ............................................................ 41 6 23.5 cautions for low-voltage detector............................ ............................................................ 4 20 chapter 24 regulator ........................................................................................................ ......... 423 24.1 outline of regulator .................................................... .................................................. .......... 423 chapter 25 mask options .................................................................................................... ....... 425 chapter 26 rom correction .................................................................................................. ... 426 26.1 functions of rom correction..................................... .......................................................... .. 426 26.2 configuration of rom correction .......................................................................................... 4 26 26.3 register controlling rom correction........................ ............................................................ 428 26.4 rom correction usage example............................................................................................ 42 9 26.5 rom correction application................................................................................................ ... 430 26.6 program execution flow.................................................................................................... ..... 433 26.7 cautions for rom correction ............................................................................................... .. 435 chapter 27 pd78f0134, 78f0138 ................................................................................................. 436 27.1 internal memory size switching register .............. ............................................................... 437 user?s manual u16228ej2v0ud 16 27.2 internal expansion ram size switching register .. .............................................................. 438 27.3 writing with flash programmer............................................................................................. . 439 27.4 programming environment................................................................................................... .. 446 27.5 communication mode........................................................................................................ ...... 446 27.6 handling of pins on board ................................................................................................. ..... 449 27.6.1 v pp pin ........................................................................................................................... ...............449 27.6.2 serial in terface pins ................................................................................................... ...................449 27.6.3 reset pin ............................................................................................................... .....................451 27.6.4 port pins............................................................................................................... .........................451 27.6.5 regc pin................................................................................................................ ......................451 27.6.6 other signal pins....................................................................................................... ....................451 27.6.7 powe r supply ............................................................................................................ ....................451 27.7 programming method ........................................................................................................ ...... 452 27.7.1 controllin g flash memory ................................................................................................ ..............452 27.7.2 flash memory programmi ng m ode ........................................................................................... ....452 27.7.3 selecting co mmunicati on mode ............................................................................................ ........453 27.7.4 communicati on commands .................................................................................................. ........454 chapter 28 instruction set................................................................................................. ...... 455 28.1 conventions used in operation list ............................ .......................................................... 45 5 28.1.1 operand identifiers and specificati on met hods ........................................................................... ..455 28.1.2 description of operation column ......................................................................................... ..........456 28.1.3 description of fl ag operati on colu mn.................................................................................... .........456 28.2 operation list ............................................................................................................ ............... 457 28.3 instructions listed by addressing type ..................... .......................................................... 465 chapter 29 electrical specifications (standard products, (a) grade products) ............................................. 468 chapter 30 electrical specifications ((a1 ) grade products) ................................ 487 chapter 31 electrical specifications ((a2 ) grade products) ................................ 506 chapter 32 package drawings ................................................................................................ 520 chapter 33 recommended soldering conditions........................................................... 523 chapter 34 cautions for wait.............................................................................................. ... 529 34.1 cautions for wait......................................................................................................... ............. 529 34.2 peripheral hardware that generates wait .................. .......................................................... 530 34.3 example of wait occurrence .......................................... ...................................................... .. 531 appendix a development tools............................................................................................... 532 a.1 software package........................................................................................................... .......... 535 a.2 language processing software.... .......................................................................................... 5 35 a.3 control software ........................................................................................................... ........... 536 user?s manual u16228ej2v0ud 17 a.4 flash memory writing tools................................................................................................. .. 536 a.5 debugging tools (hardware)...................................... ........................................................... . 537 a.5.1 when using in-circuit emulat ors ie-78k0-ns and ie-78k0- ns-a .................................................537 a.5.2 when using in-circuit emulator ie- 78k0k1- et .............................................................................5 38 a.6 debugging tools (software) ................................................................................................. .. 539 a.7 embedded software .......................................................................................................... ...... 540 appendix b notes on target system design................................................................... 541 appendix c register index .................................................................................................. ....... 548 c.1 register index (in alphabetical order with resp ect to register names) .......................... 548 c.2 register index (in alphabetical order with resp ect to register symbol)......................... 552 appendix d revision history ................................................................................................ ..... 556 d.1 major revisions in this edition ............................................................................................ . 556 user?s manual u16228ej2v0ud 18 chapter 1 outline 1.1 features minimum instruction execution time can be changed from high speed (0.2 s: @ 10 mhz operation with x1 input clock) to ultra low-speed (122 s: @ 32.768 khz operation with subsystem clock) general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) rom, ram capacities data memory item part number program memory (rom) internal high-speed ram internal expansion ram pd780131 8 kb pd780132 16 kb 512 bytes pd780133 24 kb pd780134 mask rom 32 kb 1024 bytes pd78f0134 note 1 flash memory 32 kb note 2 1024 bytes note 2 ? pd780136 48 kb pd780138 mask rom 60 kb 1024 bytes 1024 bytes pd78f0138 flash memory 60 kb note 2 1024 bytes note 2 1024 bytes note 2 notes 1. the pd78f0134 does not support the pd780136 and 780138. 2. the internal flash memory, internal high-speed ram capacities, and internal expansion ram capacities can be changed using the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) short startup is possible via the cpu default start using the on-chip ring-osc on-chip clock monitor function using on-chip ring-osc on-chip watchdog timer (operable with ring-osc clock) on-chip multiplier/divider on-chip key interrupt function on-chip clock output/buzzer output controller on-chip regulator i/o ports: 51 (n-ch open drain: 4) timer pd780131, 780132: 7 channels pd780133, 780134, 78f0134, 780136, 780138, 78f0138: 8 channels serial interface pd780131, 780132: 2 channels (uart (lin (local interconnect network)-bus supported): 1 channel, csi/uart note : 1 channel) pd780133, 780134, 78f0134, 780136, 780138, 78f0138: 3 channels (uart(lin (local interconnect network)-bus supported: 1 channel, csi/uart note : 1 channel, csi: 1 channel) note select either of the functions of these alternate-function pins. chapter 1 outline user?s manual u16228ej2v0ud 19 10-bit resolution a/d converter: 8 channels supply voltage: v dd = 2.7 to 5.5 v (standard product, (a) grade product) v dd = 3.3 to 5.5 v ((a1) grade product, (a2) grade product) operating ambient temperature: t a = ? 40 to +85 c (standard product, (a) grade product) t a = ? 40 to +105 c (flash memory version of (a1) grade product) t a = ? 40 to +110 c (mask rom version of (a1) grade product) t a = ? 40 to +125 c (mask rom version of (a2) grade product) 1.2 applications automotive equipment ? system control for body electricals (power windows, keyless entry reception, etc.) ? sub-microcontrollers for control home audio, car audio av equipment pc peripheral equipment (keyboards, etc.) household electrical appliances ? outdoor air conditioner units ? microwave ovens, electric rice cookers industrial equipment ? pumps ? vending machines ? fa (factory automation) chapter 1 outline user?s manual u16228ej2v0ud 20 1.3 ordering information (1) mask rom version (1/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 21 (1) mask rom version (2/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 22 (1) mask rom version (3/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 23 (2) flash memory version (1/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 24 (2) flash memory version (2/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 25 (2) flash memory version (3/3) part number package quality grade chapter 1 outline user?s manual u16228ej2v0ud 26 mask rom versions ( pd780131, 780132, 780133, 780134, 780136, and 780138) include mask options. when ordering, it is possible to select ?power-on-clear (poc) circuit can be used/cannot be used?, ?ring-osc clock can be stopped/cannot be stopped by software? a nd ?pull-up resistor incorporated/not incorporated in 1-bit units (p60 to p63)?. flash memory versions corresponding to the mask options of the mask rom versions are as follows. table 1-1. flash memory versions corres ponding to mask options of mask rom versions mask option poc circuit ring-osc flash memory versions (part number) cannot be stopped pd78f0134m1gb-8eu pd78f0134m1gc-8bs pd78f0134m1gk-9et pd78f0138m1gb-8eu pd78f0138m1gc-8bs pd78f0138m1gk-9et pd78f0134m1gb(a)-8eu pd78f0134m1gc(a)-8bs pd78f0134m1gk(a)-9et pd78f0138m1gb(a)-8eu pd78f0138m1gc(a)-8bs pd78f0138m1gk(a)-9et pd78f0134m1gb(a1)-8eu pd78f0134m1gc(a1)-8bs pd78f0134m1gk(a1)-9et pd78f0138m1gb(a1)-8eu pd78f0138m1gc(a1)-8bs pd78f0138m1gk(a1)-9et poc cannot be used can be stopped by software pd78f0134m2gb-8eu pd78f0134m2gc-8bs pd78f0134m2gk-9et pd78f0138m2gb-8eu pd78f0138m2gc-8bs pd78f0138m2gk-9et pd78f0134m2gb(a)-8eu pd78f0134m2gc(a)-8bs pd78f0134m2gk(a)-9et pd78f0138m2gb(a)-8eu pd78f0138m2gc(a)-8bs pd78f0138m2gk(a)-9et pd78f0134m2gb(a1)-8eu pd78f0134m2gc(a1)-8bs pd78f0134m2gk(a1)-9et pd78f0138m2gb(a1)-8eu pd78f0138m2gc(a1)-8bs pd78f0138m2gk(a1)-9et cannot be stopped pd78f0134m3gb-8eu pd78f0134m3gc-8bs pd78f0134m3gk-9et pd78f0138m3gb-8eu pd78f0138m3gc-8bs pd78f0138m3gk-9et pd78f0134m3gb(a)-8eu pd78f0134m3gc(a)-8bs pd78f0134m3gk(a)-9et pd78f0138m3gb(a)-8eu pd78f0138m3gc(a)-8bs pd78f0138m3gk(a)-9et poc used (v poc = 2.85 v 0.15 v) can be stopped by software pd78f0134m4gb-8eu pd78f0134m4gc-8bs pd78f0134m4gk-9et pd78f0138m4gb-8eu pd78f0138m4gc-8bs pd78f0138m4gk-9et pd78f0134m4gb(a)-8eu pd78f0134m4gc(a)-8bs pd78f0134m4gk(a)-9et pd78f0138m4gb(a)-8eu pd78f0138m4gc(a)-8bs pd78f0138m4gk(a)-9et cannot be stopped pd78f0134m5gb-8eu pd78f0134m5gc-8bs pd78f0134m5gk-9et pd78f0138m5gb-8eu pd78f0138m5gc-8bs pd78f0138m5gk-9et pd78f0134m5gb(a)-8eu pd78f0134m5gc(a)-8bs pd78f0134m5gk(a)-9et pd78f0138m5gb(a)-8eu pd78f0138m5gc(a)-8bs pd78f0138m5gk(a)-9et pd78f0134m5gb(a1)-8eu pd78f0134m5gc(a1)-8bs pd78f0134m5gk(a1)-9et pd78f0138m5gb(a1)-8eu pd78f0138m5gc(a1)-8bs pd78f0138m5gk(a1)-9et poc used (v poc = 3.5 v 0.2 v) can be stopped by software pd78f0134m6gb-8eu pd78f0134m6gc-8bs pd78f0134m6gk-9et pd78f0138m6gb-8eu pd78f0138m6gc-8bs pd78f0138m6gk-9et pd78f0134m6gb(a)-8eu pd78f0134m6gc(a)-8bs pd78f0134m6gk(a)-9et pd78f0138m6gb(a)-8eu pd78f0138m6gc(a)-8bs pd78f0138m6gk(a)-9et pd78f0134m6gb(a1)-8eu pd78f0134m6gc(a1)-8bs pd78f0134m6gk(a1)-9et pd78f0138m6gb(a1)-8eu pd78f0138m6gc(a1)-8bs pd78f0138m6gk(a1)-9et chapter 1 outline user?s manual u16228ej2v0ud 27 1.4 pin configuration (top view) ? 64-pin plastic lqfp (10 10) ? 64-pin plastic lqfp (14 14) ? 64-pin plastic tqfp (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p70/kr0 p71/kr1 p72/kr2 p73/kr3 p74/kr4 p75/kr5 p76/kr6 p77/kr7 p30/intp1 p140/pcl/intp6 p141/buz/intp7 p17/ti50/to50 p16/toh1/intp5 p15/toh0 p14/rxd6 p13/txd6 p12/so10 p11/si10/rxd0 p10/sck10/txd0 p60 p61 p62 p63 ev ss p40 p41 p42 p43 p50 p51 p52 p53 p00/ti000 p01/ti010/to00 p02/so11 note p03/si11 note p04/sck11 note p05/ssi11 note /ti001 note p06/ti011 note /to01 note ev dd av ref av ss ic (v pp ) v dd regc v ss x1 x2 reset xt1 xt2 p130 p120/intp0 p33/ti51/to51/intp4 p32/intp3 p31/intp2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780 138, and 78f0138. cautions 1. connect the ic (inter nally connected) pin directly to v ss . 2. connect the av ss pin to v ss . 3. connect the regc pin as follows. standard product and (a) grade product (a1) grade product and (a2) grade product when regulator is used connect to v ss via a capacitor (1 f: recommended) ? (regulator cannot be used.) when regulator is not used connect directly to v dd 4. connect the v pp pin to ev ss or v ss during normal operation. remark figures in parentheses apply to the pd78f0134 and 78f0138. chapter 1 outline user?s manual u16228ej2v0ud 28 pin identification ani0 to ani7: analog input av ref : analog reference voltage av ss : analog ground buz: buzzer output ev dd : power supply for port ev ss : ground for port ic: internally connected intp0 to intp7: external interrupt input kr0 to kr7: key return p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p43: port 4 p50 to p53: port 5 p60 to p63: port 6 p70 to p77: port 7 p120: port 12 p130: port 13 p140, p141: port 14 pcl: programmable clock output regc: regulator capacitance reset: reset rxd0, rxd6: receive data sck10, sck11 note : serial clock input/output si10, si11 note : serial data input so10, so11 note : serial data output ssi11 note : serial interface chip select input ti000, ti010, ti001 note , ti011 note , ti50, ti51: timer input to00, to01 note , to50, to51, toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v pp : programming power supply v ss : ground x1, x2: crystal oscillator (x1 input clock) xt1, xt2: crystal oscillator (subsystem clock) note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780 138, and 78f0138. chapter 1 outline user?s manual u16228ej2v0ud 29 1.5 k1 family lineup 1.5.1 78k0/kx1 product lineup pd78f0103 flash memory: 24 kb, ram: 768 bytes mask rom: 24 kb, ram: 768 bytes mask rom: 16 kb, ram: 768 bytes mask rom: 8 kb, ram: 512 bytes pd780103 pd780102 pd780101 78k0/kb1: 30-pin (7.62 mm 0.65 mm pitch) pd78f0114 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780114 pd780113 pd780112 mask rom: 8 kb, ram: 512 bytes pd780111 78k0/kc1: 44-pin (10 10 mm 0.8 mm pitch) pd78f0124 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780124 pd780123 pd780122 mask rom: 8 kb, ram: 512 bytes pd780121 78k0/kd1: 52-pin (10 10 mm 0.65 mm pitch) pd78f0148 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram: 2 kb mask rom: 32 kb, ram: 1 kb pd780148 pd780146 pd780144 mask rom: 24 kb, ram: 1 kb pd780143 78k0/kf1: 80-pin (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) pd78f0134 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780134 pd780133 pd780132 mask rom: 8 kb, ram: 512 bytes pd780131 pd78f0138 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram : 2 kb pd780138 pd780136 78k0/ke1: 64-pin (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch, 14 14 mm 0.8 mm pitch) chapter 1 outline user?s manual u16228ej2v0ud 30 the list of functions in the 78k0/kx1 is shown below. part number item 78k0/kb1 78k0/kc1 78k0/kd1 78k0/ke1 78k0/kf1 package 30 pins 44 pins 52 pins 64 pins 80 pins 16 k 8 k 24 k 8 k 24 k 8 k 24 k 48 k 24 k 48 k mask rom 8 k 24 k ? 16 k 32 k ? 16 k 32 k ? 16 k 32 k ? 60 k ? 32 k 60 k ? flash memory ? 24 k ? 32 k ? 32 k ? 32 k ? 60 k ? 60 k internal memory (bytes) ram 512 768 512 1 k 512 1 k 512 1 k 2 k 1 k 2 k power supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 0.2 s (when 10 mhz, v dd = 4.0 to 5.5 v) 0.24 s (when 8.38 mhz, v dd = 3.3 to 5.5 v) 0.4 s (when 5 mhz, v dd = 2.7 to 5.5 v) chapter 1 outline user?s manual u16228ej2v0ud 31 1.5.2 v850es/kx1 product lineup 144-pin plastic lqfp (fine pitch) (20 2 0) pd703217y pd703217 mask rom: 128 kb, ram: 6 kb i 2 c products pd703216y pd703216 mask rom: 96 kb, ram: 6 kb i 2 c products v850es/kj1 100-pin plastic lqfp (fine pitch) (14 14) pd703213y pd703213 mask rom: 96 kb, ram: 4 kb i 2 c products pd703212y pd703212 mask rom: 64 kb, ram: 4 kb i 2 c products v850es/kg1 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) pd703209y pd703209 mask rom: 96 kb, ram: 4 kb i 2 c products pd703208y pd703208 mask rom: 64 kb, ram: 4 kb i 2 c products v850es/kf1 pd70f3217y pd70f3217 flash memory: 128 kb, ram: 6 kb i 2 c products pd70f3214y pd70f3214 flash memory: 128 kb, ram: 6 kb i 2 c products pd703214y pd703214 mask rom: 128 kb, ram: 6 kb i 2 c products pd70f3210y pd70f3210 flash memory: 128 kb, ram: 6 kb i 2 c products pd703210y pd703210 mask rom: 128 kb, ram: 6 kb i 2 c products chapter 1 outline user?s manual u16228ej2v0ud 32 the list of functions in the v850es/kx1 is shown below. timer serial interface function part no. 8-bit 16-bit tmh watch wdt csi csia uart i 2 c a/d d/a rto i/o other pd703208 ? pd703208y 1 ch pd703209 ? pd703209y 1 ch pd703210 ? pd703210y 1 ch pd70f3210 ? v850es/kf1 pd70f3210y 2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch 1 ch 8 ch ? 6 ch 67 ? pd703212 ? pd703212y 1 ch pd703213 ? pd703213y 1 ch pd703214 ? pd703214y 1 ch pd70f3214 ? v850es/kg1 pd70f3214y 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch 1 ch 8 ch 2 ch 6 ch 84 ? pd703216 ? pd703216y 2 ch pd703217 ? pd703217y 2 ch pd70f3217 ? v850es/kj1 pd70f3217y 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch 2 ch 16 ch 2 ch 12 ch 128 ? chapter 1 outline user?s manual u16228ej2v0ud 33 1.6 block diagram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 78k/0 cpu core internal high-speed ram rom (flash memory) v ss , ev ss ic (v pp ) v dd , ev dd serial interface csi10 si10/p11 so10/p12 sck10/p10 ani0/p20 to ani7/p27 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 8 a/d converter rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 8 system control reset x1 x2 clock monitor power on clear/ low voltage indicator reset control port 6 p60 to p63 4 port 7 p70 to p77 port 12 p120 port 13 p130 8 p40 to p43 4 p50 to p53 4 port 14 p140, p141 2 ring-osc xt1 xt2 16-bit timer/ note event counter 01 to01 note /ti011 note /p06 ti001 note /p05 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi11 note si11 note /p03 so11 note /p02 sck11 note /p04 ssi11 note /p05 intp5/p16 intp6/p140, intp7/p141 2 buzzer output buz/p141 clock output control pcl/p140 key return 8 kr0/p70 to kr7/p77 multiplier & divider voltage regulator regc poc/lvi control note chapter 1 outline user?s manual u16228ej2v0ud 34 1.7 outline of functions (1/2) item ? ? ? ? ? chapter 1 outline user?s manual u16228ej2v0ud 35 (2/2) item ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? user?s manual u16228ej2v0ud 36 chapter 2 pin functions 2.1 pin function list there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 v dd pins other than port pins (1) port pins (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. chapter 2 pin functions user?s manual u16228ej2v0ud 37 (1) port pins (2/2) pin name i/o function after reset alternate function p40 to p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p60 to p63 i/o port 6. 4-bit i/o port (n-ch open drain). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. input ? p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input kr0 to kr7 p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? p140 pcl/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input buz/intp7 chapter 2 pin functions user?s manual u16228ej2v0ud 38 (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 p120 intp1 to intp3 p30 to p32 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p141/buz si10 p11/rxd0 si11 note input serial data input to serial interface input p03 so10 p12 so11 note output serial data output from serial interface input p02 sck10 p10/txd0 sck11 note i/o clock input/output for serial interface input p04 ssi11 note input serial interface chip select input input p05/ti001 rxd0 p11/si10 rxd6 input serial data input to asynch ronous serial interface input p14 txd0 p10/sck10 txd6 output serial data output from asyn chronous serial interface input p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 note external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 note ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 note input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input p06/to01 note to00 16-bit timer/event counter 00 output p01/ti010 to01 note output 16-bit timer/event counter 01 output input p06/ti011 note ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input p33/to51/intp4 to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input p16/intp5 pcl output clock output (for trimming of x1 i nput clock, subsystem clock) input p140/intp6 buz output buzzer output input p141/intp7 ani0 to ani7 input a/d converter analog input input p20 to p27 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. chapter 2 pin functions user?s manual u16228ej2v0ud 39 (2) non-port pins (2/2) pin name i/o function after reset alternate function av ref input a/d converter reference voltage input and positive power supply for port 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 2 pin functions user?s manual u16228ej2v0ud 40 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 function as a 7-bit i/o port. these pins also function as timer i/o, serial interface data i/o, clock i/o, and chip select input. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as a 7-bit i/o port. p00 to p06 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o, serial inte rface data i/o, clock i/o, and chip select input. (a) ti000, ti001 note these are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the captur e registers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 note these are the pins for inputting a capture trigger signal to the capture register (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 note these are timer output pins. (d) si11 note this is a serial interface serial data input pin. (e) so11 note this is a serial interface serial data output pin. (f) sck11 note this is the serial interf ace serial clock i/o pin. (g) ssi11 note this is the serial interface chip select input pin. note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the chapter 2 pin functions user?s manual u16228ej2v0ud 41 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. t hese pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, cl ock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial interface serial data input pin. (b) so10 this is a serial interface serial data output pin. (c) sck10 this is a serial interface serial clock i/o pin. (d) rxd0, rxd6 these are the serial data input pins of the asynchronous serial interface. (e) txd0, txd6 these are the serial data output pins of the asynchronous serial interface. (f) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (g) to50, toh0, and toh1 these are timer output pins. (h) intp5 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit input-only port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit input-only port. (2) control mode p20 to p27 function as a/d converter analog input pins (a ni0 to ani7). when using these pins as analog input pins, see (5) ani0/p20 to ani7/p27 in 12.6 cautions for a/d converter . chapter 2 pin functions user?s manual u16228ej2v0ud 42 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also f unction as pins for external interrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interru pt request input pins and timer i/o pins. (a) intp1 to intp4 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (c) to51 this is a timer output pin. 2.2.5 p40 to p43 (port 4) p40 to p43 function as a 4- bit i/o port. p40 to p43 can be set to inpu t or output in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). 2.2.6 p50 to p53 (port 5) p50 to p53 function as a 4- bit i/o port. p50 to p53 can be set to inpu t or output in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). 2.2.7 p60 to p63 (port 6) p60 to p63 function as a 4-bit i/o port. p60 to p63 can be set to input port or output por t in 1-bit units using port mode register 6 (pm6). p60 to p63 are n-ch open-drain pins. use of an on-chip pu ll-up resistor can be specified by a mask option only for mask rom versions. 2.2.8 p70 to p77 (port 7) p70 to p77 function as an 8-bit i/o port. these pins also function as key interrupt input pins. the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an 8-bit i/o port. p70 to p77 can be set to input or output in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input pins. chapter 2 pin functions user?s manual u16228ej2v0ud 43 2.2.9 p120 (port 12) p120 functions as a 1-bit i/o port. this pin also func tions as a pin for external interrupt request input. the following operation modes can be specified. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to inpu t or output using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 functions as an external interrupt request input pi n (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.10 p130 (port 13) p130 functions as a 1-bit output-only port. 2.2.11 p140 and p141 (port 14) p140 and p141 function as a 2-bit i/o port. these pins al so function as external interrupt request input, clock output, and buzzer output pins. the following operation modes can be specified in 1-bit units. (1) port mode p140 and p141 function as a 2-bit i/o port. p140 and p141 c an be set to input or output in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 and p141 function as external interrupt request input, clock output, and buzzer output pins. (a) intp6, intp7 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pcl this is a clock output pin. (c) buz this is a buzzer output pin. 2.2.12 av ref this is the a/d converter reference voltage input pin. when the a/d converter is not used, connect this pin directly to ev dd or v dd note . note connect port 2 directly to ev dd when it is used as a digital port. 2.2.13 av ss this is the a/d converter ground potential pin. even when the a/d converter is not used, always use this pin with the same potential as the ev ss pin or v ss pin. chapter 2 pin functions user?s manual u16228ej2v0ud 44 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting the capacitor for the regul ator. when using the regulator, connect this pin to v ss via a capacitor (1 chapter 2 pin functions user?s manual u16228ej2v0ud 45 2.3 pin i/o circuits and recommended connection of unused pins table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. refer to figure 2-1 for the configurat ion of the i/o circuit of each type. table 2-2. pin i/o circuit types pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 p02/so11 note p03/si11 note p04/sck11 note p05/ssi11 note /ti001 note p06/ti011 note /to01 note p10/sck10/txd0 p11/si10/rxd0 8-a p12/so10 p13/txd6 5-a p14/rxd6 8-a p15/toh0 5-a p16/toh1/intp5 p17/ti50/to50 8-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0 to p27/ani7 9-c input connect to ev dd or ev ss . p30/intp1 to p32/intp3 p33/ti51/to51/intp4 8-a p40 to p43 p50 to p53 5-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p60, p61 (mask rom version) 13-s p60, p61 (flash memory version) 13-r p62, p63 (mask rom version) 13-v p62, p63 (flash memory version) 13-w input: connect to ev ss . output: leave this pin open at low-level output after clearing the output latch of the port to 0. p70/kr0 to p77/kr7 p120/intp0 8-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p130 3-c output leave open. p140/pcl/intp6 p141/buz/intp7 8-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. chapter 2 pin functions user?s manual u16228ej2v0ud 46 table 2-2. pin i/o circuit types (2/2) note connect port 2 directly to ev dd when it is used as a digital port. pin name i/o circuit type i/o recommended connection of unused pins reset 2 ? xt1 input connect directly to ev dd or v dd . xt2 16 leave open. av ref connect directly to ev dd or v dd note . av ss ic connect directly to ev ss or v ss . v pp ? ? connect to ev ss or v ss . chapter 2 pin functions user?s manual u16228ej2v0ud 47 figure 2-1. pin i/o circuit list (1/2) type 3-c type 2 type 8-a type 5-a type 9-c schmitt-triggered input with hysteresis characteristics in pullup enable data output disable ev dd p-ch v dd p-ch in/out n-ch ev dd p-ch n-ch data out in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + ? pullup enable data output disable input enable ev dd p-ch v dd p-ch in/out n-ch data output disable in/out n-ch type 13-r chapter 2 pin functions user?s manual u16228ej2v0ud 48 figure 2-1. pin i/o circuit list (2/2) type 13-v type 13-s type 13-w type 16 data output disable in/out n-ch ev dd mask option ? ? ? ? ? ? data output disable in/out n-ch input enable middle-voltage input buffer data output disable in/out n-ch ev dd mask option ? ? ? ? ? ? input enable middle-voltage input buffer p-ch feedback cut-off xt1 xt2 user?s manual u16228ej2v0ud 49 chapter 3 cpu architecture 3.1 memory space products in the 78k0/ke1 can each access a 64 kb memory s pace. figures 3-1 to 3-8 show the memory maps. caution regardless of the internal memory capacity, the initial valu es of the internal memory size switching register (ims) and inte rnal expansion ram size switching register (ixs) of all products in the 78k0/ke1 are fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. table 3-1. set values of internal memo ry size switching register (ims) and internal expansion ram si ze switching register (ixs) ims ixs pd780131 42h pd780132 44h pd780133 c6h pd780134 c8h 0ch pd78f0134 note value corresponding to mask rom version pd780136 cch pd780138 cfh 0ah pd78f0138 value corresponding to mask rom version note the pd78f0134 does not support the pd780136 and 780138. chapter 3 cpu architecture user?s manual u16228ej2v0ud 50 figure 3-1. memory map ( pd780131) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 8192 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 1 h 0 0 0 0 h f f f 1 h 0 0 0 2 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 51 figure 3-2. memory map ( pd780132) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 16384 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 3 h 0 0 0 0 h f f f 3 h 0 0 0 4 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 52 figure 3-3. memory map ( pd780133) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 5 h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 53 figure 3-4. memory map ( pd780134) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 32768 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 7 h 0 0 0 0 h f f f 7 h 0 0 0 8 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 54 figure 3-5. memory map ( pd78f0134) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 32768 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 7 h 0 0 0 0 h f f f 7 h 0 0 0 8 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 55 figure 3-6. memory map ( pd780136) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh f400h f3ffh c000h bfffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh bfffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 49152 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 56 figure 3-7. memory map ( pd780138) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh f400h f3ffh f000h efffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh efffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 57 figure 3-8. memory map ( pd78f0138) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh f400h f3ffh f000h efffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh efffh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 58 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/ke1 products incorporate internal rom (ma sk rom or flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity chapter 3 cpu architecture user?s manual u16228ej2v0ud 59 3.1.2 internal data memory space 78k0/ke1 products incorporate the following rams. (1) internal high-speed ram table 3-4. internal high-speed ram capacity part number internal high-speed ram pd780131 pd780132 512 8 bits (fd00h to feffh) pd780133 pd780134 pd78f0134 pd780136 pd780138 pd78f0138 1024 8 bits (fb00h to feffh) the 32-byte area fee0h to feffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per one bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram table 3-5. internal expansion ram capacity part number internal expansion ram pd780131 pd780132 pd780133 pd780134 pd78f0134 ? pd780136 pd780138 pd78f0138 1024 8 bits (f400h to f7ffh) the internal expansion ram can also be used as a normal dat a area similar to the internal high-speed ram, as well as a program area in which inst ructions can be written and executed. 3.1.3 special function register (sfr) area on-chip peripheral hardware special function registers (sfr s) are allocated in the area ff00h to ffffh (refer to table 3-6 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. chapter 3 cpu architecture user?s manual u16228ej2v0ud 60 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/ke1, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-9 to 3-16 show corresponde nce between data memory and addressing. for details of each addressing mode, refer to 3.4 operand address addressing . figure 3-9. correspondence between data memory and addressing ( pd780131) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 8192 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 1 h 0 0 0 2 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 61 figure 3-10. correspondence between data memory and addressing ( pd780132) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 16384 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 3 h 0 0 0 4 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 62 figure 3-11. correspondence between data memory and addressing ( pd780133) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 63 figure 3-12. correspondence between data memory and addressing ( pd780134) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 7 h 0 0 0 8 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 64 figure 3-13. correspondence between data memory and addressing ( pd78f0134) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 7 h 0 0 0 8 h f f a f h 0 0 b f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f chapter 3 cpu architecture user?s manual u16228ej2v0ud 65 figure 3-14. correspondence between data memory and addressing ( pd780136) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh c000h bfffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 49152 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 66 figure 3-15. correspondence between data memory and addressing ( pd780138) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 67 figure 3-16. correspondence between data memory and addressing ( pd78f0138) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh f800h f7ffh f400h f3ffh fb00h faffh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing reserved internal expansion ram 1024 8 bits chapter 3 cpu architecture user?s manual u16228ej2v0ud 68 3.2 processor registers the 78k0/ke1 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, the pc is automat ically incremented according to the numbe r of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-17. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents ar e automatically stacked upon interrupt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset input sets the psw to 02h. figure 3-18. format of program status word 7 0 psw ie z rbs1 ac rbs0 0 isp cy (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. other interrupt requests are all disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgement is controlled with an in-service priority flag (isp), an in terrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgement and is set (1) upon ei instruction execution. chapter 3 cpu architecture user?s manual u16228ej2v0ud 69 (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable mask able vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (refer to 17.3 (3) priority specifi cation flag registers (pr0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgement is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-19. format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-20 and 3-21. caution since reset input makes the sp contents undefi ned, be sure to initialize the sp before using the stack. chapter 3 cpu architecture user?s manual u16228ej2v0ud 70 figure 3-20. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u16228ej2v0ud 71 figure 3-21. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u16228ej2v0ud 72 3.2.2 general-purpose registers general-purpose registers are mapp ed at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are se t by the cpu control instruction (sel rbn). because of the 4-register bank configur ation, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-22. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h chapter 3 cpu architecture user?s manual u16228ej2v0ud 73 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like general -purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-6 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a re served word in the ra78k0, and is defined by the header file ?sfrbit.h? in the cc78k0. when us ing the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input. chapter 3 cpu architecture user?s manual u16228ej2v0ud 74 table 3-6. special function register list (1/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 3 cpu architecture user?s manual u16228ej2v0ud 75 table 3-6. special function register list (2/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff2ch port mode register 12 pm12 r/w ? ffh ff2eh port mode register 14 pm14 r/w ? ffh ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff34h pull-up resistor option register 4 pu4 r/w ? 00h ff35h pull-up resistor option register 5 pu5 r/w ? 00h ff37h pull-up resistor option register 7 pu7 r/w ? 00h ff38h ff39h correction address register 0 note 1 corad0 r/w ? ? 0000h ff3ah ff3bh correction address register 1 note 1 corad1 r/w ? ? 0000h ff3ch pull-up resistor option register 12 pu12 r/w ? 00h ff3eh pull-up resistor option register 14 pu14 r/w ? 00h ff40h clock output selection register cks r/w ? 00h ff41h 8-bit timer compare register 51 cr51 r/w ? ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff48h external interrupt risi ng edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h ff4ah serial i/o shift register 11 note 2 sio11 r ? ? 00h ff4ch transmit buffer register 11 note 2 sotb11 r/w ? ? undefined ff4fh input switch control register isc r/w ? 00h ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff53h asynchronous serial inte rface reception error status register 6 asis6 r ? ? 00h ff55h asynchronous serial in terface transmission status register 6 asif6 r ? ? 00h ff56h clock selection register 6 cksr6 r/w ? ? 00h ff57h baud rate generator control register 6 brgc6 r/w ? ? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ? 16h ff60h sdr0l ? 00h ff61h remainder data register 0 sdr0 sdr0h r ? 00h ff62h mda0ll ? 00h ff63h mda0l mda0lh r/w ? 00h ff64h mda0hl ? 00h ff65h multiplication/division data register a0 mda0h mda0hh r/w ? 00h ff66h mdb0l ? 00h ff67h multiplication/division data register b0 mdb0 mdb0h r/w ? 00h notes 1. pd780136, 780138, and 78f0138 only. 2. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. chapter 3 cpu architecture user?s manual u16228ej2v0ud 76 table 3-6. special function register list (3/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff68h multiplier/divider control register 0 dmuc0 r/w ? 00h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h ff6ah timer clock selection register 50 tcl50 r/w ? ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ? 00h ff6dh 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h ff6eh key return mode register krm r/w ? 00h ff6fh watch timer operation mode register wtm r/w ? 00h ff70h asynchronous serial interface operation mode register 0 asim0 r/w ? 01h ff71h baud rate generator control register 0 brgc0 r/w ? ? 1fh ff72h receive buffer register 0 rxb0 r ? ? ffh ff73h asynchronous serial inte rface reception error status register 0 asis0 r ? ? 00h ff74h transmit shift register 0 txs0 w ? ? ffh ff80h serial operation mode register 10 csim10 r/w ? 00h ff81h serial clock select ion register 10 csic10 r/w ? 00h ff84h transmit buffer register 10 sotb10 r/w ? ? undefined ff88h serial operation mode register 11 note 1 csim11 r/w ? 00h ff89h serial clock selection register 11 note 1 csic11 r/w ? 00h ff8ah correction control register note 1 corcn r/w ? 00h ff8ch timer clock selection register 51 tcl51 r/w ? ? 00h ff98h watchdog timer mode register wdtm r/w ? ? 67h ff99h watchdog timer enable register wdte r/w ? ? 9ah ffa0h ring-osc mode register rcm r/w ? 00h ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 00h ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? ? 05h ffa9h clock monitor mode register clm r/w ? 00h ffach reset control flag register resf r ? ? 00h note 2 ffb0h ffb1h 16-bit timer counter 01 note 1 tm01 r ? ? 0000h ffb2h ffb3h 16-bit timer capture/compare register 001 note 1 cr001 r/w ? ? 0000h ffb4h ffb5h 16-bit timer capture/compare register 011 note 1 cr011 r/w ? ? 0000h ffb6h 16-bit timer mode control register 01 note 1 tmc01 r/w ? 00h notes 1. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. 2. this value varies depending on the reset source. chapter 3 cpu architecture user?s manual u16228ej2v0ud 77 table 3-6. special function register list (4/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffb7h prescaler mode register 01 note 1 prm01 r/w ? 00h ffb8h capture/compare control register 01 note 1 crc01 r/w ? 00h ffb9h 16-bit timer output control register 01 note 1 toc01 r/w ? 00h ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h ffbfh low-voltage detection level selection register lvis r/w ? ? 00h ffe0h interrupt request flag register 0l if0 if0l r/w 00h ffe1h interrupt request flag register 0h if0h r/w 00h ffe2h interrupt request flag register 1l if1 if1l r/w 00h ffe3h interrupt request flag register 1h if1h r/w 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ffh ffe7h interrupt mask flag register 1h mk1h r/w dfh ffe8h priority specification flag register 0l pr0 pr0l r/w ffh ffe9h priority specification flag register 0h pr0h r/w ffh ffeah priority specification flag register 1l pr1 pr1l r/w ffh ffebh priority specification flag register 1h pr1h r/w ffh fff0h internal memory size switching register note 2 ims r/w ? ? cfh fff4h internal expansion ram size switching register note 2 ixs r/w ? ? 0ch fffbh processor clock control register pcc r/w ? 00h notes 1. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. 2. the default value of ims and ixs are fixed (ims = cfh, ixs = 0ch) in all products in the 78k0/ke1 regardless of the internal memory capacity. therefore, set the following value to each product. ims ixs pd780131 42h pd780132 44h pd780133 c6h pd780134 c8h 0ch pd78f0134 note value corresponding to mask rom version pd780136 cch pd780138 cfh 0ah pd78f0138 value corresponding to mask rom version note the pd78f0134 does not support the pd780136 and 780138. chapter 3 cpu architecture user?s manual u16228ej2v0ud 78 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the num ber of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for deta ils of instructions, refer to 78k/0 series instructions user?s manual (u12326e) . 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transferre d to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of rela tive branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... chapter 3 cpu architecture user?s manual u16228ej2v0ud 79 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branc hed to the entire memory s pace. the callf !addr11 instruction is branc hed to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 chapter 3 cpu architecture user?s manual u16228ej2v0ud 80 3.3.3 table indirect addressing [function] table contents (branch desti nation address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be s pecified with an instruction word are tr ansferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u16228ej2v0ud 81 3.4 operand address addressing the following methods are available to specify the r egister and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/ke1 instruction words, the followi ng instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the pr oduct of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. chapter 3 cpu architecture user?s manual u16228ej2v0ud 82 3.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register bank select flags (rbs0 to rbs1) and the register specify co des (rn and rpn) of an operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1100010 register specify code incw de; when selecting de register pair as rp operation code 1 0000100 register specify code chapter 3 cpu architecture user?s manual u16228ej2v0ud 83 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code chapter 3 cpu architecture user?s manual u16228ej2v0ud 84 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture r egisters of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] shown below. [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring valu e of a register to saddr (fe30h) operation code 1 1110010 op c ode 0 0110000 30h (s addr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 chapter 3 cpu architecture user?s manual u16228ej2v0ud 85 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op c ode 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u16228ej2v0ud 86 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand addre ss for addressing the memory. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de chapter 3 cpu architecture user?s manual u16228ej2v0ud 87 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the conten ts of the base register, that is, the hl register pair in the register bank specified by the r egister bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offs et data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory + 10 chapter 3 cpu architecture user?s manual u16228ej2v0ud 88 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the regist er bank specified by the register ba nk select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perf ormed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] (selecting b register) operation code 10101011 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory chapter 3 cpu architecture user?s manual u16228ej2v0ud 89 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] in the case of push de (saving de register) operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u16228ej2v0ud 90 chapter 4 port functions 4.1 port functions there are two types of pin i/o buffer power supplies: av ref and ev dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 78k0/ke1 products are provided with the ports shown in fi gure 4-1, which enable vari ety of control operations. the functions of each port are shown in table 4-2. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, refer to chapter 2 pin functions . figure 4-1. port types port 2 p20 p27 port 3 p30 p33 port 5 p50 p53 port 0 p00 p06 port 1 p10 p17 port 4 p40 p43 port 6 p60 p63 port 7 p70 p77 p120 port 12 port 14 p140 p141 p130 port 13 chapter 4 port functions user?s manual u16228ej2v0ud 91 table 4-2. port functions (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p60 to p63 i/o port 6. 4-bit i/o port (n-ch open drain). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. input ? p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input kr0 to kr7 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. chapter 4 port functions user?s manual u16228ej2v0ud 92 table 4-2. port functions (2/2) pin name i/o function after reset alternate function p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? ? ? chapter 4 port functions user?s manual u16228ej2v0ud 93 4.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o , serial interface data i/o, and clock i/o. reset input sets port 0 to input mode. figures 4-2 to 4-5 show block diagrams of port 0. caution when p02/so11 note , p03/si11 note , and p04/sck11 note are used as genera l-purpose ports, do not write to serial clock selection register 11 (csic11). figure 4-2. block diagra m of p00, p03, and p05 p00/ti000, p03/si11 note , p05/ssi11 note /ti001 note wr pu rd wr port wr pm pu00, pu03, pu05 alternate function output latch (p00, p03, p05) pm00, pm03, pm05 ev dd p-ch selector internal bus pu0 pm0 note available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 94 figure 4-3. block diagram of p01 and p06 p01/ti010/to00, p06/ti011 note /to01 note wr pu rd wr port wr pm pu01, pu06 alternate function output latch (p01, p06) pm01, pm06 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the chapter 4 port functions user?s manual u16228ej2v0ud 95 figure 4-4. block diagram of p02 p02/so11 note wr pu rd wr port wr pm pu02 output latch (p02) pm02 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 96 figure 4-5. block diagram of p04 p04/sck11 note wr pu rd wr port wr pm pu04 alternate function output latch (p04) pm04 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 97 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset input sets port 1 to input mode. figures 4-6 to 4-10 show block diagrams of port 1. caution when p10/sck10/txd0, p11/si10/rxd0, and p 12/so10 are used as general-purpose ports, do not write to serial clock selection register 10 (csic10). figure 4-6. block diagram of p10 p10/sck10/txd0 wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 98 figure 4-7. block diagram of p11 and p14 p11/si10/rxd0, p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 99 figure 4-8. block diagram of p12 and p15 p12/so10 p15/toh0 wr pu rd wr port wr pm pu12, pu15 output latch (p12, p15) pm12, pm15 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr chapter 4 port functions user?s manual u16228ej2v0ud 100 figure 4-9. block diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function ev dd p-ch internal bus selector pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 101 figure 4-10. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 102 4.2.3 port 2 port 2 is an 8-bit input-only port. this port can also be used for a/d converter analog input. figure 4-11 shows a block diagram of port 2. figure 4-11. block di agram of p20 to p27 rd a/d converter p20/ani0 to p27/ani7 internal bus rd: read signal chapter 4 port functions user?s manual u16228ej2v0ud 103 4.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when used as an input por t, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resist or option register 3 (pu3). this port can also be used for external interrupt request input. reset input sets port 3 to input mode. figures 4-12 and 4-13 show block diagrams of port 3. figure 4-12. block di agram of p30 to p32 p30/intp1 to p32/intp3 wr pu rd wr port wr pm pu30 to pu32 alternate function output latch (p30 to p32) pm30 to pm32 ev dd p-ch selector internal bus pu3 pm3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 104 figure 4-13. blo ck diagram of p33 p33/intp4/ti51/to51 wr pu rd wr port wr pm pu33 alternate function output latch (p33) pm33 alternate function ev dd p-ch selector internal bus pu3 pm3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 105 4.2.5 port 4 port 4 is a 4-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (pu4). reset input sets port 4 to input mode. figure 4-14 shows a block diagram of port 4. figure 4-14. block diag ram of p40 to p43 rd p-ch wr pu wr port wr pm ev dd p40 to p43 pu40 to pu43 output latch (p40 to p43) pm40 to pm43 selector internal bus pu4 pm4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr chapter 4 port functions user?s manual u16228ej2v0ud 106 4.2.6 port 5 port 5 is a 4-bit i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (pu5). reset input sets port 5 to input mode. figure 4-15 shows a block diagram of port 5. figure 4-15. block diag ram of p50 to p53 rd p-ch wr pu wr port wr pm ev dd p50 to p53 pu50 to pu53 output latch (p50 to p53) pm50 to pm53 selector internal bus pu5 pm5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 107 4.2.7 port 6 port 6 is a 4-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). this port has the following functions for pull-up resistor s. these functions differ d epending on whether the product is a mask rom version or a flash memory version. table 4-4. pull-up resistor of port 6 pins p60 to p63 mask rom version an on-chip pull-up resistor can be specified in 1-bit units by mask option flash memory version on-chip pu ll-up resistors are not provided the p60 to p63 pins are n-ch open-drain pins. reset input sets port 6 to input mode. figure 4-16 shows a block diagram of port 6. figure 4-16. block diag ram of p60 to p63 rd p60 to p63 wr port wr pm output latch (p60 to p63) pm60 to pm63 selector ev dd mask option resistor ? ? ? ? ? ? ? ? ? ? internal bus mask rom versions only no pull-up resistor for flash memory versions pm6 pm6: port mode register 6 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 108 4.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). this port can also be used for key return input. reset input sets port 7 to input mode. figure 4-17 shows a block diagram of port 7. figure 4-17. block di agram of p70 to p77 p70/kr0 to p77/kr7 wr pu rd wr port wr pm pu70 to pu77 alternate function output latch (p70 to p77) pm70 to pm77 ev dd p-ch selector internal bus pu7 pm7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 109 4.2.9 port 12 port 12 is a 1-bit i/o port with an out put latch. port 12 can be set to the input mode or output mo de in 1-bit units using port mode register 12 (pm12). when used as an inpu t port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used for external interrupt input. reset input sets port 12 to input mode. figure 4-18 shows a block diagram of port 12. figure 4-18. blo ck diagram of p120 p120/intp0 wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch selector internal bus pu12 pm12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 110 4.2.10 port 13 port 13 is a 1-bit output-only port. figure 4-19 shows a block diagram of port 13. figure 4-19. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level immediately after reset is released, the output signal of p130 can be dummy-output as the reset signal to the cpu. chapter 4 port functions user?s manual u16228ej2v0ud 111 4.2.11 port 14 port 14 is a 2-bit i/o port with an out put latch. port 14 can be set to the input mode or output mo de in 1-bit units using port mode register 14 (pm14). when the p140 and p141 pins are used as an input port, use of an on-chip pull- up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for external interr upt request input, buzzer output, and clock output. reset input sets port 14 to input mode. figure 4-20 shows a block diagram of port 14. figure 4-20. block di agram of p140 and p141 p140/pcl/intp6, p141/buz/intp7 wr pu rd wr port wr pm pu140, pu141 alternate function output latch (p140, p141) pm140, pm141 alternate function ev dd p-ch selector internal bus pu14 pm14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal chapter 4 port functions user?s manual u16228ej2v0ud 112 4.3 registers controlling port function port functions are controlled by the following three types of registers. ? port mode registers (pm0, pm1, pm3 to pm7, pm12, pm14) ? port registers (p0 to p7, p12 to p14) ? pull-up resistor option registers (pu0 , pu1, pu3 to pu5, pu7, pu12, pu14) (1) port mode registers (pm0, pm1, pm3 to pm7, pm12, and pm14) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used as alternate-function pins, set th e port mode register and output latch as shown in table 4-4. figure 4-21. format of port mode register 7 1 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 ff21h ffh r/w 7 1 pm3 6 1 5 1 4 1 3 pm33 2 pm32 1 pm31 0 pm30 ff23h ffh r/w 7 1 pm4 6 1 5 1 4 1 3 pm43 2 pm42 1 pm41 0 pm40 ff24h ffh r/w 7 1 pm5 6 1 5 1 4 1 3 pm53 2 pm52 1 pm51 0 pm50 ff25h ffh r/w 7 1 pm6 6 1 5 1 4 1 3 pm63 2 pm62 1 pm61 0 pm60 ff26h ffh r/w 7 pm77 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 ff27h ffh r/w 7 1 pm12 6 1 5 1 4 1 3 1 2 1 1 1 0 pm120 ff2ch ffh r/w 7 1 pm14 6 1 5 1 4 1 3 1 2 1 1 pm141 0 pm140 ff2eh ffh r/w pmmn pmn pin i/o mode selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 4 port functions user?s manual u16228ej2v0ud 113 table 4-5. settings of port mode register and output latch when using alternate function alternate function pin name function name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 p02 so11 note output 0 0 p03 si11 note input 1 input 1 p04 sck11 note output 0 1 ssi11 note input 1 p05 ti001 note input 1 ti011 note input 1 p06 to01 note output 0 0 input 1 sck10 output 0 1 p10 txd0 output 0 1 si10 input 1 p11 rxd0 input 1 p12 so10 output 0 0 p13 txd6 output 0 1 p14 rxd6 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 p30 to p32 intp1 to intp3 input 1 intp4 input 1 ti51 input 1 p33 to51 output 0 0 p70 to p77 kr0 to kr7 input 1 p120 intp0 input 1 pcl output 0 0 p140 intp6 input 1 buz output 0 0 p141 intp7 input 1 note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. remark : don?t care pm : port mode register p : port output latch chapter 4 port functions user?s manual u16228ej2v0ud 114 (2) port registers (p0 to p7, p12 to p14) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h (but p2 is undefined). figure 4-22. format of port register 7 0 symbol p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 ff01h 00h (output latch) r/w r 7 p27 p2 6 p26 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 ff02h undefined 7 0 p3 6 0 5 0 4 0 3 p33 2 p32 1 p31 0 p30 ff03h 00h (output latch) r/w 7 0 p4 6 0 5 0 4 0 3 p43 2 p42 1 p41 0 p40 ff04h 00h (output latch) r/w 7 0 p5 6 0 5 0 4 0 3 p53 2 p52 1 p51 0 p50 ff05h 00h (output latch) r/w 7 0 p6 6 0 5 0 4 0 3 p63 2 p62 1 p61 0 p60 ff06h 00h (output latch) r/w 7 p77 p7 6 p76 5 p75 4 p74 3 p73 2 p72 1 p71 0 p70 ff07h 00h (output latch) r/w 7 0 p12 6 0 5 0 4 0 3 0 2 0 1 0 0 p120 ff0ch 00h (output latch) r/w 7 0 p13 6 0 5 0 4 0 3 0 2 0 1 0 0 p130 ff0dh 00h (output latch) r/w 7 0 p14 6 0 5 0 4 0 3 0 2 0 1 p141 0 p140 ff0eh 00h (output latch) r/w m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level chapter 4 port functions user?s manual u16228ej2v0ud 115 (3) pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, and pu14) these registers specify whether the on-ch ip pull-up resistors of p00 to p06, p 10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, or p140 and p141 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to wh ich the use of an on-chip pull-up resistor has been specified in pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. on-chip pu ll-up resistors cannot be connected to bits set to output mode and bits used as alternate-functi on output pins, regardless of the settings of pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution use of a pull-up resistor can be specified for p60 to p63 pins by a mask option only in the mask rom versions. figure 4-23. format of pull-up resistor option register 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w 7 pu17 pu1 6 pu16 5 pu15 4 pu14 3 pu13 2 pu12 1 pu11 0 pu10 ff31h 00h r/w 7 0 pu3 6 0 5 0 4 0 3 pu33 2 pu32 1 pu31 0 pu30 ff33h 00h r/w 7 0 pu4 6 0 5 0 4 0 3 pu43 2 pu42 1 pu41 0 pu40 ff34h 00h r/w 7 0 pu5 6 0 5 0 4 0 3 pu53 2 pu52 1 pu51 0 pu50 ff35h 00h r/w 7 pu77 pu7 6 pu76 5 pu75 4 pu74 3 pu73 2 pu72 1 pu71 0 pu70 ff37h 00h r/w 7 0 pu12 6 0 5 0 4 0 3 0 2 0 1 0 0 pu120 ff3ch 00h r/w 7 0 pu14 6 0 5 0 4 0 3 0 2 0 1 pu141 0 pu140 ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions user?s manual u16228ej2v0ud 116 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. caution in the case of 1-bit memory manipulation instruction, althou gh a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer inst ruction, and the output latch contents are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. user?s manual u16228ej2v0ud 117 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three syst em clock oscillator s are available. ? ? ? chapter 5 clock generator user?s manual u16228ej2v0ud 118 figure 5-1. block diagra m of clock generator x1 x2 f xp f xt frc xt1 xt2 f x 2 2 stop mstop f x 2 3 f x 2 4 f x 2 4 rstop css pcc2 cls mcm0 mcs cls mcc osts1 osts0 osts2 1/2 3 most 16 most 15 most 14 most 13 most 11 c p u f r f x pcc1 pcc0 x1 oscillator internal bus ring-osc mode register (rcm) main osc control register (moc) internal bus ring-osc oscillator mask option 1: cannot be stopped 0: can be stopped cpu clock (f cpu ) controller processor clock control register (pcc) main clock mode register (mcm) x1 oscillation stabilization time counter oscillation stabilization time select register (osts) oscillation stabilization time counter status register (ostc) clock to peripheral hardware prescaler operation clock switch 8-bit timer h1, watchdog timer prescaler prescaler selector subsystem clock oscillator watch clock, clock output function f cpu control signal chapter 5 clock generator user?s manual u16228ej2v0ud 119 5.3 registers controlling clock generator the following six registers are used to control the clock generator. ? ? ? ? ? ? chapter 5 clock generator user?s manual u16228ej2v0ud 120 figure 5-2. format of processor clock control register (pcc) address: fffbh after reset: 00h r/w note 1 symbol <7> <6> <5> <4> 3 2 1 0 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc control of x1 oscillator operation note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock f eedback resistor selection 0 on-chip feedback resistor used 1 on-chip feedback resistor not used note 3 cls cpu clock status 0 x1 input clock or ring-osc clock 1 subsystem clock notes 1. bit 5 is read-only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the x1 oscillator operation. when the cpu is operating on the ring- osc clock, use bit 7 (mstop) of the main osc control register (moc) to stop the x1 oscillator operation (this cannot be set by mcc). a stop instruction should not be used. 3. this bit can be set to 1 only when the subsystem clock is not used. 4. be sure to switch css from 1 to 0 when bits 1 (mcs) and 0 (mcm0) of the main clock mode register (mcm) are 1. caution be sure to clear bit 3 to 0. cpu clock (f cpu ) selection css note 4 pcc2 pcc1 pcc0 mcm0 = 0 mcm0 = 1 0 0 0 f x f r f xp 0 0 1 f x /2 f r /2 f xp /2 0 1 0 f x /2 2 f r /2 2 f xp /2 2 0 1 1 f x /2 3 f r /2 3 f xp /2 3 0 1 0 0 f x /2 4 f r /2 4 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f xt /2 other than above setting prohibited chapter 5 clock generator user?s manual u16228ej2v0ud 121 remarks 1. mcm0: bit 0 of the main clock mode register (mcm) 2. f x : main system clock oscillation frequency (x1 input clock oscillation frequency or ring-osc clock oscillation frequency) 3. f r : ring-osc clock oscillation frequency 4. f xp : x1 input clock oscillation frequency 5. f xt : subsystem clock oscillation frequency the fastest instruction can be executed in 2 clocks of t he cpu clock in the 78k0/ke1. therefore, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in the table 5-2. table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) x1 input clock note (at 10 mhz operation) ring-osc clock note (at 240 khz (typ.) operation) subsystem clock (at 32.768 khz operation) f x 0.2 s 8.3 s (typ.) ? f x /2 0.4 s 16.6 s (typ.) ? f x /2 2 0.8 s 33.2 s (typ.) ? f x /2 3 1.6 s 66.4 s (typ.) ? f x /2 4 3.2 s 132.8 s (typ.) ? f xt /2 ? ? 122.1 s note the main clock mode register (mcm) is used to set the cpu clock (x1 input clock/ring-osc clock) (see figure 5-4 ). (2) ring-osc mode register (rcm) this register sets the operation mode of ring-osc. this register is valid when ?can be stopped by software? is set for ring-osc by a mask option, and the x1 input clock or subsystem clock is selected as the cpu clock. if ?cannot be stopped? is selected for ring-osc by a mask option, settings for this register are invalid. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-3. format of ring-osc mode register (rcm) address: ffa0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> rcm 0 0 0 0 0 0 0 rstop rstop ring-osc oscillating/stopped 0 ring-osc oscillating 1 ring-osc stopped caution make sure that the bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting rstop. chapter 5 clock generator user?s manual u16228ej2v0ud 122 (3) main clock mode register (mcm) this register sets the cpu clo ck (x1 input clock/ring-osc clock). mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-4. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 2 <1> <0> mcm 0 0 0 0 0 0 mcs mcm0 mcs cpu clock status 0 operates with ring-osc clock 1 operates with x1 input clock mcm0 selection of clock supplied to cpu 0 ring-osc clock 1 x1 input clock note bit 1 is read-only. cautions 1. when ring-osc clo ck is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hard ware with ring-osc clock cannot be guaranteed. therefore, when ring-osc cl ock is selected as the clock supplied to the cpu, do not use peripheral hardwa re. in addition, stop the peripheral hardware before switching the clock supplied to the cpu from the x1 input clock to the ring-osc clock. note, however, th at the following peripheral hardware can be used when the cpu ope rates on the ring-osc clock. ? watchdog timer ? clock monitor ? 8-bit timer h1 when f r /2 7 is selected as count clock ? peripheral hardware selecting ext ernal clock as the clock source (except when external count clock of tm 0n (n = 0, 1) is selected (ti00n valid edge)) 2. set mcs = 1 and mcm0 = 1 before s witching subsystem clock operation to x1 input clock operation (bit 4 (css) of th e processor clock cont rol register (pcc) is changed from 1 to 0). chapter 5 clock generator user?s manual u16228ej2v0ud 123 (4) main osc control register (moc) this register selects the operat ion mode of the x1 input clock. this register is used to stop the x1 oscillator operation when the cpu is operating with the ring-osc clock. therefore, this register is valid only when t he cpu is operating with the ring-osc clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-5. format of main osc control register (moc) address: ffa2h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 mstop control of x1 oscillator operation 0 x1 oscillator operating 1 x1 oscillator stopped cautions 1. make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting mstop. 2. to stop x1 oscillation wh en the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control regi ster (pcc) to 1 (setting by mstop is not possible). chapter 5 clock generator user?s manual u16228ej2v0ud 124 (5) oscillation stabilization time c ounter status register (ostc) this is the status register of the x1 input clock oscillati on stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock o scillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, clock monitor, and wdt), the stop instruction, mstop = 1, and mcc = 1 clear ostc to 00h. figure 5-6. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 1 0 0 0 0 2 11 /f xp min. (204.8 s min.) 1 1 0 0 0 2 13 /f xp min. (819.2 s min.) 1 1 1 0 0 2 14 /f xp min. (1.64 ms min.) 1 1 1 1 0 2 15 /f xp min. (3.27 ms min.) 1 1 1 1 1 2 16 /f xp min. (6.55 ms min.) cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. if the stop mode is entered and then released while the ring-osc is being used as the cpu clock, set the oscilla tion stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization ti me counter counts up to the oscillation stabilization time set by osts. note, ther efore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 3. the wait time when stop mode is re leased does not include the time after stop mode release until clock oscillation star ts (?a? below) regardless of whether stop mode is released by reset input or interr upt generation. stop mode release x1 pin voltage waveform a remarks 1. values in parentheses are reference values for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency chapter 5 clock generator user?s manual u16228ej2v0ud 125 (6) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabilization wait time when stop mode is released. the wait time set by osts is valid only after stop mo de is released with the x1 input clock selected as cpu clock. after stop mode is released with ring-osc selected as cpu clock, the oscillation stabilization time must be confirmed by ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 5-7. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0 0 1 2 11 /f xp (204.8 s) 0 1 0 2 13 /f xp (819.2 s) 0 1 1 2 14 /f xp (1.64 ms) 1 0 0 2 15 /f xp (3.27 ms) 1 0 1 2 16 /f xp (6.55 ms) other than above setting prohibited cautions 1. if the stop mode is entered and then released wh ile the ring-osc is being used as the cpu clock, set the oscilla tion stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization ti me counter counts up to the oscillation stabilization time set by osts. note, ther efore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 2. the wait time when stop mode is re leased does not include the time after stop mode release until clock oscillation star ts (?a? below) regardless of whether stop mode is released by reset input or interr upt generation. stop mode release x1 pin voltage waveform a remarks 1. values in parentheses are reference values for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency chapter 5 clock generator user?s manual u16228ej2v0ud 126 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator osc illates with a crystal resonator or ceramic resonator (standard: 8.38 mhz, 10 mhz when regc pin is directly connected to v dd ) connected to the x1 and x2 pins. an external clock can be input to the x1 oscillator when the regc pin is directly connected to v dd . in this case, input the clock signal to the x1 pin and in put the inverse signal to the x2 pin. figure 5-8 shows examples of the exte rnal circuit of the x1 oscillator. figure 5-8. examples of extern al circuit of x1 oscillator (a) crystal, ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator external clock x1 x2 5.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator when the re gc pin is directly connected to v dd . in this case, input the clock signal to the xt 1 pin and the inverse signal to the xt2 pin. figure 5-9 shows examples of an external ci rcuit of the subsystem clock oscillator. figure 5-9. examples of external ci rcuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz xt1 xt2 external clock cautions are listed on the next page. chapter 5 clock generator user?s manual u16228ej2v0ud 127 cautions 1. when using the x1 os cillator and subsys tem clock oscillator, wire as follows in the area enclosed by the broken lines in the figure 5-10 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the os cillator capacitor the same potential as v ss . do not ground the capacitor to a ground patter n through which a high current flows. do not fetch signals from the oscillator. note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. figure 5-10 shows examples of in correct resonator connection. figure 5-10. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. chapter 5 clock generator user?s manual u16228ej2v0ud 128 figure 5-10. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in paralle l, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. chapter 5 clock generator user?s manual u16228ej2v0ud 129 5.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect directly to ev dd or v dd xt2: leave open in this state, however, some current may leak via the on-chip feedback resist or of the subsystem clock oscillator when the x1 input clock and ring-osc clock stop. to minimi ze leakage current, the above on-chip feedback resistor can be set not to be used via bit 6 (frc) of the processor clo ck control register (pcc). in this case also, connect the xt1 and xt2 pins as described above. figure 5-11. subsystem cl ock feedback resistor frc p-ch feedback resistor xt1 xt2 remark the feedback resistor is required to control the bias point of the osci llation waveform so that the bias point is in the middle of the power supply voltage. 5.4.4 ring-osc oscillator ring-osc oscillator is incorporated in the 78k0/ke1. ?can be stopped by software? or ?cannot be stopped? can be selected by a mask option. the ring-osc clock always oscillates after reset release (240 khz (typ.)). 5.4.5 prescaler the prescaler generates va rious clocks by dividing the x1 oscillator output when the x1 input clock is selected as the clock to be supplied to the cpu. caution when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing th e ring-osc oscillator output (f x = 240 khz (typ.)). chapter 5 clock generator user?s manual u16228ej2v0ud 130 5.5 clock generator operation the clock generator generates the following clocks and contro ls the operation modes of the cpu, such as standby mode. ? x1 input clock f xp ? ring-osc clock f r ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the cpu starts operation when the on-ch ip ring-osc oscillator starts outputting after reset release in the 78k0/ke1, thus enabling the following. (1) enhancement of security function when the x1 input clock is set as t he cpu clock by the default setting, the device cannot operate if the x1 input clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the on-chip ring- osc clock, so the device can be started by the ring-osc clock after reset release by the clock monitor (detection of x1 input cl ock stop). consequently, the system can be safely shut down by performing a minimum operation, such as a cknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started without waiting for the x1 input clock oscillation stabilization time, the total performance can be improved. a timing diagram of the cpu default start using ring-osc is shown in figure 5-12. chapter 5 clock generator user?s manual u16228ej2v0ud 131 figure 5-12. timing diagram of cpu default start using ring-osc ring-osc clock (f r ) cpu clock x1 input clock (f xp ) operation stopped: 17/f r x1 oscillation stabilization time: 2 11 /f xp to 2 16 /f xp note reset ring-osc clock x1 input clock switched by software subsystem clock (f xt ) note check using the oscillation stabilization time counter status register (ostc). (a) when the reset signal is generated, bit 0 of the main clock mode register (mcm) is set to 0 and the ring- osc clock is set as the cpu clock. however, a clo ck is supplied to the cpu a fter 17 clocks of the ring-osc clock have elapsed after reset release (or clock su pply to the cpu stops for 17 clocks). during the reset period, oscillation of the x1 in put clock and ring-osc clock is stopped. (b) after reset release, the cpu clock can be switched fr om the ring-osc clock to the x1 input clock using bit 0 (mcm0) of the main clock mode register (mcm) after t he x1 input clock oscillation stabilization time has elapsed. at this time, check the o scillation stabilization time using the oscillation stabilization time counter status register (ostc) bef ore switching the cpu clock. the cpu clock status can be checked using bit 1 (mcs) of mcm. (c) ring-osc can be set to stopped/oscillating using t he ring-osc mode register (rcm) when ?can be stopped by software? is selected for the ring-osc by a mask opti on, if the x1 input or sub system clock is used as the cpu clock. make sure that mcs is 1 at this time. (d) when ring-osc is used as the cpu clock, the x1 in put clock can be set to stopped/oscillating using the main osc control register (moc). make sure that mcs is 0 at this time. when the subsystem clock is used as the cpu clock, wh ether the x1 input clock stops or oscillates can be set by the processor clock control register (pcc). in addition, halt mode can be used during operation with the subsystem clock, but stop mode cannot be used (s ubsystem clock oscillation cannot be stopped by the stop instruction). (e) select the x1 input clock oscillation stabilization time (2 11 /f xp , 2 13 /f xp , 2 14 /f xp , 2 15 /f xp , 2 16 /f xp ) using the oscillation stabilization time select register (osts) when releasing stop mode while x1 input clock is being used as the cpu clock. in addition, when releasing stop mode while reset is released and ring-osc is being used as the cpu clock, check the x1 input clock os cillation stabilization time using the oscillation stabilization time counter status register (ostc). chapter 5 clock generator user?s manual u16228ej2v0ud 132 a status transition diagram of this product is shown in figure 5-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscill ation status of each clock are shown in tables 5-3 and 5-4, respectively. figure 5-13. status transition diagram (1/4) (1) when ?ring-osc can be stopped by software? is selected by mask option (when subsystem clock is not used) status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt reset release interrupt interrupt halt instruction stop instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction halt instruction stop note 4 reset note 5 notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 3. when shifting from status 2 to stat us 1, make sure that mcs is 0. 4. when ?ring-osc can be stopped by software? is selected by a mask option, the watchdog timer stops operating in the ha lt and stop modes, regardless of the s ource clock of the watchdog timer. however, oscillation of ring-osc does not stop ev en in the halt and stop modes if rstop = 0. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u16228ej2v0ud 133 figure 5-13. status transition diagram (2/4) (2) when ?ring-osc can be stopped by software? is selected by mask option (when subsystem clock is used) halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt interrupt halt instruction halt instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcc = 0 css = 0 note 5 mcc = 1 css = 1 note 5 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction stop note 4 reset note 6 status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating reset release interrupt halt instruction status 6 cpu clock: f xt f xp : oscillation stopped f r : oscillating/ oscillation stopped status 5 cpu clock: f xt f xp : oscillating f r : oscillating/ oscillation stopped notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 3. when shifting from status 2 to stat us 1, make sure that mcs is 0. 4. when ?ring-osc can be stopped by software? is se lected by a mask option, the clock supply to the watchdog timer is stopped after the halt or stop in struction has been executed, regardless of the setting of bit 0 (rstop) of the ring-osc mode register (rcm) and bit 0 (mcm0) of the main clock mode register (mcm). 5. the operation cannot be shifted between subsyst em clock operation and ring-osc operation. 6. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u16228ej2v0ud 134 figure 5-13. status transition diagram (3/4) (3) when ?ring-osc cannot be stop ped? is selected by mask option (when subsystem clock is not used) status 3 cpu clock: f xp f xp : oscillating f r : oscillating halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 4 status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 2. when shifting from status 2 to stat us 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ?ring-osc cannot be stopped? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using the tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an internal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u16228ej2v0ud 135 figure 5-13. status transition diagram (4/4) (4) when ?ring-osc cannot be stop ped? is selected by mask option (when subsystem clock is used) halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 5 interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release mcc = 0 css = 0 note 5 mcc = 1 css = 1 note 4 interrupt interrupt halt instruction halt instruction status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 5 cpu clock: f xt f xp : oscillation stopped f r : oscillating status 4 cpu clock: f xt f xp : oscillating f r : oscillating notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 2. when shifting from status 2 to stat us 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ?ring-osc cannot be stopped? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using the tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an internal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. the operation cannot be shifted between subsyst em clock operation and ring-osc operation. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u16228ej2v0ud 136 table 5-3. relationship between operat ion clocks in each operation status x1 oscillator ring-osc oscillator note 2 prescaler clock supplied to peripherals status operation mode mstop = 0 mcc = 0 mstop = 1 mcc = 1 note 1 rstop = 0 rstop = 1 subsystem clock oscillator cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating stopped oscillating oscillating stopped oscillating note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) table 5-4. oscillation control fl ags and clock oscillation status x1 oscillator ring-osc oscillator rstop = 0 stopped oscillating mstop = 1 note rstop = 1 setting prohibited rstop = 0 oscillating mstop = 0 note rstop = 1 oscillating stopped rstop = 0 oscillating mcc = 1 note rstop = 1 stopped stopped rstop = 0 oscillating mcc = 0 note rstop = 1 oscillating stopped note setting x1 oscillator oscillating/stopped differs depending on the cpu clock used. ? when the ring-osc clock is used as the cpu clock: set using the mstop bit ? when the subsystem clock is used as the cpu clock: set using the mcc bit caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm) chapter 5 clock generator user?s manual u16228ej2v0ud 137 5.6 time required to switch betwee n ring-osc clock and x1 input clock bit 0 (mcm0) of the main clock mode register (mcm) is used to switch between the ring-osc clock and x1 input clock. in the actual switching operation, s witching does not occur immediately after mcm0 rewrite; several instructions are executed using the pre-switch clock after switching mcm0 (see table 5-5 ). bit 1 (mcs) of mcm is used to judge that operation is per formed using either the ring-osc clock or x1 input clock. to stop the original clock af ter switching the clock, wait for the nu mber of clocks shown in table 5-5 before stopping. table 5-5. time required to switch be tween ring-osc clock and x1 input clock pcc time required for switching pcc2 pcc1 pcc0 x1 ring-osc ring-osc x1 0 0 0 f xp /f r + 1 clock 0 0 1 f xp /2f r + 1 clock 0 1 0 f xp /4f r + 1 clock 0 1 1 f xp /8f r + 1 clock 1 0 0 f xp /16f r + 1 clock 2 clocks caution to calculate the maximum time, set f r = 120 khz. remarks 1. pcc: processor clock control register 2. f xp : x1 input clock oscillation frequency 3. f r : ring-osc clock oscillation frequency 4. the maximum time is the number of cl ocks of the cpu cloc k before switching. chapter 5 clock generator user?s manual u16228ej2v0ud 138 5.7 time required for cpu clock switchover the cpu clock can be switched using bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operat ion is not performed immediately after rewr iting to the pcc; operation continues on the pre-switchover clock for several instructions (see table 5-6 ). whether the system is operat ing on the x1 input clock (or ring-osc clock) or the subsystem clock can be ascertained using bit 5 (cls) of the pcc register. table 5-6. maximum time requi red for cpu clock switchover set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css p cc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks f xp /f xt clocks (306 clocks) 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /2f xt clocks (153 clocks) 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /4f xt clocks (77 clocks) 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /8f xt clocks (39 clocks) 0 1 0 0 1 clock 1 cloc k 1 clock 1 clock f xp /16f xt clocks (20 clocks) 1 1 clock 1 clock 1 cl ock 1 cloc k 1 clock remarks 1. the maximum time is the number of cl ocks of the pre-switchover cpu clock. 2. figures in parentheses apply to operation with f xp = 10 mhz and f xt = 32.768 khz. caution selection of the cpu clock cycle division factor (pcc0 to pcc2) and switchover from the x1 input clock to the subsystem clock (changi ng css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the cpu clo ck cycle division factor (pcc0 to pcc2) and switchover from the subsystem clock to th e x1 input clock (changing css from 1 to 0). chapter 5 clock generator user?s manual u16228ej2v0ud 139 5.8 clock switching flowchart and register setting 5.8.1 switching from ring-o sc clock to x1 input clock figure 5-14. switching from ring-osc clock to x1 input clock (flowchart) ; f cpu = f r ; ring-osc oscillation ; ring-osc clock operation ; x1 oscillation ; oscillation stabilization time status register ; oscillation stabilization time f xp /2 16 mcm.1 (mcs) is changed from 0 to 1 ; x1 oscillation stabilization time status check x1 oscillation stabilization time has elapsed x1 oscillation stabilization time has not elapsed pcc = 00h rcm = 00h mcm = 00h moc = 00h ostc = 00h osts = 05h note ostc check note each processing after reset pcc setting mcm.0 1 x1 input clock operation ring-osc clock operation (dividing set pcc) register value after reset ring-osc clock operation x1 input clock note check the oscillation stabilization wait time of the x1 osci llator after reset release using the ostc register and then switch to the x1 input clock operation after t he oscillation stabilization wait time has elapsed. the osts register setting is valid only after stop mode is released by interrupt during x1 input clock operation. chapter 5 clock generator user?s manual u16228ej2v0ud 140 5.8.2 switching from x1 in put clock to ring-osc clock figure 5-15. switching from x1 input clock to ring-osc clock (flowchart) mcm.1 (mcs) is changed from 1 to 0 ; ring-osc oscillating ; ring-osc oscillating? ring-osc clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation no: rstop = 0 yes: rstop = 1 pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h rcm.0 note (rstop) = 1? rstop = 0 mcm0 0 register setting in x1 input clock operation x1 input clock operation ring-osc clock operation note required only when ?clock can be stopped by software? is selected for ring-osc by a mask option. chapter 5 clock generator user?s manual u16228ej2v0ud 141 5.8.3 switching from x1 in put clock to subsystem clock figure 5-16. switching from x1 input clock to subsystem clock (flowchart) mcs = 1 not changed. cls is changed from 0 to 1. ; subsystem clock operation subsystem clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h css 1 note register setting in x1 input clock operation x1 input clock operation subsystem clock note set css to 1 after confirming that oscillat ion of the subsystem clock is stabilized. chapter 5 clock generator user?s manual u16228ej2v0ud 142 5.8.4 switching from subsyst em clock to x1 input clock figure 5-17. switching from subsystem clock to x1 input clock (flowchart) ; subsystem clock operation ; x1 oscillating? ; x1 oscillation enabled ; wait for x1 oscillation stabilization time ; x1 input clock operation cls is changed from 1 to 0. mcs = 1 not changed. x1 oscillation stabilization time elapsed x1 oscillation stabilization time not elapsed yes: x1 oscillation stopped no: x1 oscillating mcc 0 pcc.4 (css) = 1 mcm = 03h mcc = 1? ostc check css 0 x1 input clock operation subsystem clock operation x1 input clock operation chapter 5 clock generator user?s manual u16228ej2v0ud 143 5.8.5 register settings the table below shows the statuses of the setting flags and status flags when each mode is set. table 5-7. clock and register setting setting flag status flag pcc register mcm register moc register rcm register pcc register mcm register f cpu mode mcc css mcm0 mstop rstop note 1 cls mcs ring-osc oscillating 0 0 1 0 0 0 1 x1 input clock note 2 ring-osc stopped 0 0 1 0 1 0 1 x1 oscillating 0 0 0 0 0 0 0 ring-osc clock x1 stopped 0 note 3 0 0 1 0 0 0 x1 oscillating, ring-osc oscillating 0 1 1 note 5 0 note 6 0 1 1 x1 stopped, ring-osc oscillating 1 1 1 note 5 0 note 6 0 1 1 x1 oscillating, ring-osc stopped 0 1 1 note 5 0 note 6 1 1 1 subsystem clock note 4 x1 stopped, ring-osc stopped 1 1 1 note 5 0 note 6 1 1 1 notes 1. valid only when ?clock can be stopped by software? is selected for ring-osc by a mask option. 2. do not set mcc = 1 or mstop = 1 during x1 input clo ck operation (even if mcc = 1 or mstop = 1 is set, the x1 oscillation does not stop). 3. do not set mcc = 1 during ring-osc operation (even if mcc = 1 is set, the x1 oscillation does not stop). to stop x1 oscillation during ring-osc operation, use mstop. 4. shifting to subsystem clock operation mode must be performed from the x1 input clock operation mode. from subsystem clock operation mode, only x1 input clock operation mode can be shifted to. 5. do not set mcm0 = 0 (shifting to ring-osc) during subsystem clock operation. 6. do not set mstop = 1 during subsystem clock operati on (even if mstop = 1 is set, x1 oscillation does not stop). to stop x1 oscillation duri ng subsystem clock operation, use mcc. user?s manual u16228ej2v0ud 144 chapter 6 16-bit timer/even t counters 00 and 01 the pd780131 and 780132 incorporate 16-bi t timer/event counter 00, and the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 incorporate 16 -bit timer/event counters 00 and 01. 6.1 functions of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 note have the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output (1) interval timer 16-bit timer/event counters 00 and 01 generate an in terrupt request at the preset time interval. (2) ppg output 16-bit timer/event counters 00 and 01 can output a recta ngular wave whose frequency and output pulse width can be set freely. (3) pulse width measurement 16-bit timer/event counters 00 and 01 can measure th e pulse width of an externally input signal. (4) external event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (5) square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (6) one-shot pulse output 16-bit timer event counters 00 and 01 can output a one-sh ot pulse whose output pulse width can be set freely. note available only for the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 145 6.2 configuration of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. table 6-1. configuration of 16- bit timer/event counters 00 and 01 item configuration timer counter 16 bits (tm0n) register 16-bit timer capture/compar e register: 16 bits (cr00n, cr01n) timer input ti00n, ti01n timer output to0n, output controller control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0 (pm0) port register 0 (p0) remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figures 6-1 and 6-2 show the block diagrams. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f x f x /2 2 f x /2 8 f x ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p01) pm01 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 146 figure 6-2. block diagram of 16-bit timer/event counter 01 ( chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 147 (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. figure 6-3. format of 16-bit timer counter 0n (tm0n) tm0n (n = 0, 1) symbol ff11h (tm00) ffb1h (tm01) ff10h (tm00) ffb0h (tm01) address: ff10h, ff11h (tm00), ffb0h, ffb1h (tm01) after reset: 0000h r the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of ti00n is input in the mode in wh ich clear & start occurs when inputting the valid edge of ti00n <4> if tm0n and cr00n match in the mode in which cl ear & start occurs on a match of tm0n and cr00n <5> ospt0n is set in one-shot pulse output mode (2) 16-bit timer capture/comp are register 00n (cr00n) cr00n is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or as a comp are register is set by bit 0 (crc0n0) of capture/compar e control register 0n (crc0n). cr00n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 6-4. format of 16-bit timer ca pture/compare register 00n (cr00n) cr00n (n = 0, 1) symbol ff13h (cr000) ffb3h (cr001) ff12h (cr000) ffb2h (cr001) address: ff12h, ff13h (cr000), ffb2h, ffb3h (cr001) after reset: 0000h r/w ? ? chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 148 table 6-2. cr00n capture trigger and valid edges of ti00n and ti01n pins (1) ti00n pin valid edge selected as captu re trigger (crc0n1 = 1, crc0n0 = 1) ti00n pin valid edge cr00n capture trigger es0n1 es0n0 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01n pin valid edge selected as captu re trigger (crc0n1 = 0, crc0n0 = 1) ti01n pin valid edge cr00n capture trigger es1n1 es1n0 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es0n1, es0n0 = 1, 0 and es1n1, es1n0 = 1, 0 is prohibited. 2. es0n1, es0n0: bits 5 and 4 of prescaler mode register 0n (prm0n) es1n1, es1n0: bits 7 and 6 of prescaler mode register 0n (prm0n) crc0n1, crc0n0: bits 1 and 0 of capture/ compare control register 0n (crc0n) 3. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 cautions 1. set a value other than 0000h in cr00n in the mode in which clear & start occurs on a match of tm0n and cr00n. however, in the free-r unning mode and in the clear mode using the valid edge of ti00n, if cr00n is cleared to 0000h, an interrupt request (inttm00n) is generated when the value of cr00n chang es from 0000h to 0001h following overflow (ffffh). 2. when p01 or p06 is used as the valid edge input pin of ti01n, it cannot be used as the timer output (to0n). moreover, when p01 or p06 is used as to0n, it cannot be used as the valid edge input pin of ti01n. 3. when cr00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the captu re data itself is the correct value). if count stop input and capture trigger in put conflict, the capture d data is undefined. 4. do not rewrite cr00n during tm0n operation. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 149 (3) 16-bit timer capture/comp are register 01n (cr01n) cr01n is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or a compare register is set by bit 2 (crc0n2) of capture/ compare control register 0n (crc0n). cr01n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 6-5. format of 16-bit timer ca pture/compare register 01n (cr01n) cr01n (n = 0, 1) symbol ff15h (cr010) ffb5h (cr011) ff14h (cr010) ffb4h (cr011) address: ff14h, ff15h (cr010), ffb4h, ffb5h (cr011) after reset: 0000h r/w ? when cr01n is used as a compare register the value set in the cr01n is cons tantly compared with 16-bit timer c ounter 0n (tm0n) count value, and an interrupt request (inttm01n) is gener ated if they match. the set valu e is held until cr01n is rewritten. ? when cr01n is used as a capture register it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n valid edge is set by prescaler mode register 0n (prm0n) (see table 6-3 ). table 6-3. cr01n capture trigger and valid edge of ti00n pin (crc0n2 = 1) ti00n pin valid edge cr01n capture trigger es0n1 es0n0 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es0n1, es0n0 = 1, 0 is prohibited. 2. es0n1, es0n0: bits 5 and 4 of prescaler mode register 0n (prm0n) crc0n2: bit 2 of capture/compar e control register 0n (crc0n) 3. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 cautions 1. if the cr01n register is cleared to 000 0h, an interrupt request (i nttm01n) is generated after the tm0n register overflows, after the timer is cleared and started on a match between the tm0n register and the cr00n register, or after th e timer is cleared by th e valid edge of ti00n or a one-shot trigger. 2. when cr01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the captu re data itself is the correct value). if count stop input and capture trigger in put conflict, the capture d data is undefined. 3. cr01n can be rewritten dur ing tm0n operation. for details, see caution 2 in figure 6-20. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 150 6.3 registers controlling 16-bi t timer/event counters 00 and 01 the following six registers are used to cont rol 16-bit timer/event counters 00 and 01. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? port mode register 0 (pm0) ? port register 0 (p0) (1) 16-bit timer mode cont rol register 0n (tmc0n) this register sets the 16-bit timer operating mode, th e 16-bit timer counter 0n (tm0n) clear mode, and output timing, and detects an overflow. tmc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0n to 00h. caution 16-bit timer counter 0n (tm0n) starts opera tion at the moment tmc0n2 and tmc0n3 are set to values other than 0, 0 (operation stop mode), respectively. set tmc0n2 and tmc0n3 to 0, 0 to stop the operation. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 151 figure 6-6. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 <0> ovf00 symbol tmc00 address ffbah after reset: 00h r/w tmc003 tmc002 tmc001 operating mode and clear mode selection to00 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 0 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 1 0 0 1 0 1 clear & start occurs on ti000 valid edge ? 1 1 0 clear & start occurs on match between tm00 and cr000 match between tm00 and cr000 or match between tm00 and cr010 1 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge generated on match between tm00 and cr000, or match between tm00 and cr010 ovf00 16-bit timer counter 00 (tm00) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf00 flag. 2. set the valid edge of the ti000/p00 pin using prescaler mode register 00 (prm00). 3. if any the following modes: the mode in which clear & star t occurs on match between tm00 and cr000, the mode in which clear & start o ccurs at the ti00 valid edge, or free-running mode is selected, when the set value of cr0 00 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remark to00: 16-bit timer/event counter 00 output pin ti000: 16-bit timer/event counter 00 input pin tm00: 16-bit timer counter 00 cr000: 16-bit timer capture/compare register 000 cr010: 16-bit timer capture/compare register 010 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 152 figure 6-7. format of 16-bit timer mode control register 01 (tmc01) 7 0 6 0 5 0 4 0 3 tmc013 2 tmc012 1 tmc011 <0> ovf01 symbol tmc01 address ffb6h after reset: 00h r/w tmc013 tmc012 tmc011 operating mode and clear mode selection to01 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm01 cleared to 0) no change not generated 0 1 0 free-running mode match between tm01 and cr001 or match between tm01 and cr011 0 1 1 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge 1 0 0 1 0 1 clear & start occurs on ti001 valid edge ? 1 1 0 clear & start occurs on match between tm01 and cr001 match between tm01 and cr001 or match between tm01 and cr011 1 1 1 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge generated on match between tm01 and cr001, or match between tm01 and cr011 ovf01 16-bit timer counter 01 (tm01) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf01 flag. 2. set the valid edge of the ti001/p05 pin using prescaler mode register 01 (prm01). 3. if any the following modes: the mode in which clear & star t occurs on match between tm01 and cr001, the mode in which clear & start o ccurs at the ti01 valid edge, or free-running mode is selected, when the set value of cr0 01 is ffffh and the tm01 value changes from ffffh to 0000h, the ovf01 flag is set to 1. remark to01: 16-bit timer/event counter 01 output pin ti001: 16-bit timer/event counter 01 input pin tm01: 16-bit timer counter 01 cr001: 16-bit timer capture/compare register 001 cr011: 16-bit timer capture/compare register 011 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 153 (2) capture/compare control register 0n (crc0n) this register controls the oper ation of the 16-bit timer capture/ compare registers (cr00n, cr01n). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0n to 00h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 6-8. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 1 captures on valid edge of ti000 by reverse phase crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc00. 2. when the mode in which clear & start occurs on a match betw een tm00 and cr000 is selected with 16-bit timer mode control register 00 (tmc00), cr0 00 should not be specified as a capture register. 3. the capture operation is not performed if both the rising and falling edges ar e specified as the valid edge of ti000. 4. to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by pr escaler mode register 00 (prm00). chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 154 figure 6-9. format of capture/comp are control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 1 captures on valid edge of ti001 by reverse phase crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc01. 2. when the mode in which clear & start occurs on a match betw een tm01 and cr001 is selected with 16-bit timer mode control register 01 (tmc01), cr0 01 should not be specified as a capture register. 3. the capture operation is not performed if both the rising and falling edges ar e specified as the valid edge of ti001. 4. to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by pr escaler mode register 01 (prm01). (3) 16-bit timer output control register 0n (toc0n) this register controls the operation of the 16-bit timer/ event counter 0n output controller. it sets/resets the timer output f/f (lv0n), enables/disables output inversio n and 16-bit timer/event counter 0n timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0n to 00h. remark n = 0: chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 155 figure 6-10. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 vali d edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possi ble because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than toc004. 2. if lvs00 and lvr00 are read, 0 is read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 00 (prm00) is required to write to ospt00 successively. 6. do not set lvs00 to 1 before toe00, and do not set lvs00 and toe00 to 1 simultaneously. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 156 figure 6-11. format of 16-bit timer ou tput control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe01 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc014 timer output f/f control using match of cr011 and tm01 0 disables inversion operation 1 enables inversion operation lvs01 lvr01 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc011 timer output f/f control using match of cr001 and tm01 0 disables inversion operation 1 enables inversion operation toe01 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti001 vali d edge. in the mode in which clear & start occurs on a match between the tm01 register and cr001 register, one-shot pulse output is not possi ble because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than toc014. 2. if lvs01 and lvr01 are read, 0 is read. 3. ospt01 is automatically cleared after data is set, so 0 is read. 4. do not set ospt01 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 01 (prm01) is required to write to ospt01 successively. 6. do not set lvs01 to 1 before toe01, and do not set lvs01 and toe01 to 1 simultaneously. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 157 (4) prescaler mode register 0n (prm0n) this register is used to set the 16-bit timer counter 0n (tm0n) count clock and ti00n and ti01n input valid edges. prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears prm0n to 00h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 6-12. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 0 0 f x (10 mhz) 0 1 f x /2 2 (2.5 mhz) 1 0 f x /2 8 (39.06 khz) 1 1 ti000 valid edge note note the external clock requires a pulse two cycles longer than internal count clock (f x ). chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 158 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 16-bit timer/ev ent counter 00 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the ring-osc clock is supplied as the samplin g clock to eliminate noise. 2. always set data to prm00 a fter stopping the timer operation. 3. if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti 000 and the capture trigger. 4. if the ti000 or ti010 pin is high level immediatel y after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to en able the operation of 16-bit timer counter 00 (tm00). care is therefore required when pulli ng up the ti000 or ti010 pin. however, when re- enabling operation after the operation has b een stopped once, the rising edge is not detected. 5. when p01 is used as the ti010 valid edge, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge. remarks 1 . f x : x1 input clock oscillation frequency 2. ti000, ti010: 16-bit timer/ event counter 00 input pin 3. figures in parentheses are for operation with f x = 10 mhz. figure 6-13. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm011 prm010 count clock selection 0 0 f x (10 mhz) 0 1 f x /2 4 (625 khz) 1 0 f x /2 6 (156.25 khz) 1 1 ti001 valid edge note note the external clock requires a pulse two cycles longer than internal count clock (f x ). chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 159 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 16-bit timer/ev ent counter 01 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 01 is not guaranteed, either, because the ring-osc clock is supplied as the samplin g clock to eliminate noise. 2. always set data to prm01 a fter stopping the timer operation. 3. if the valid edge of ti001 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti 001 and the capture trigger. 4. if the ti001 or ti011 pin is high level immediatel y after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti001 pin or ti011 pin to en able the operation of 16-bit timer counter 01 (tm01). care is therefore required when pulli ng up the ti001 or ti011 pin. however, when re- enabling operation after the operation has b een stopped once, the rising edge is not detected. 5. when p06 is used as the ti011 valid edge, it cannot be used as the timer output (to01), and when used as to01, it cannot be used as the ti011 valid edge. remarks 1 . f x : x1 input clock oscillation frequency 2. ti001, ti011: 16-bit timer/ event counter 01 input pin 3. figures in parentheses are for operation with f x = 10 mhz. (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 and p06/to01 note /ti011 note pins for timer output, set pm01 and pm06 and the output latch of p01 and p06 to 0. when using the p01/to 00/ti010 and p06/to01 note /ti011 note pins for timer input, set pm01 and pm06 to 0. at this time, the output latch of p01 and p06 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 6-14. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) note available only for the chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 160 6.4 operation of 16-bit ti mer/event counters 00 and 01 6.4.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 6-15 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 6-15 for the set value). <2> set any value to the cr00n register. <3> set the count clock by using the prm0n register. <4> set the tmc0n register to start the operation (see figure 6-15 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remark for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (cr00n) as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set in cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 161 figure 6-15. control register setti ngs for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. 2. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 162 figure 6-16. interval ti mer configuration diagram 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) ovf0n clear circuit inttm00n f x (f x ) note 1 f x /2 2 (f x /2 4 ) note 1 f x /2 8 (f x /2 6 ) note 1 ti000/p00 (ti001/p05) note 1 selector noise eliminator f x note 2 notes 1. frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. 2. ovf0n is set to 1 only when 16-bit timer capt ure/compare register 00n is set to ffffh. figure 6-17. timing of interval timer operation count clock t tm0n count value cr00n inttm00n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged remark interval time = (n + 1) t n = 0001h to ffffh n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 163 6.4.2 ppg output operations setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 6-18 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 6-18 for the set value). <2> set any value to the cr00n register as the cycle. <3> set any value to the cr01n register as the duty factor. <4> set the toc0n register (see figure 6-18 for the set value). <5> set the count clock by using the prm0n register. <6> set the tmc0n register to start the operation (see figure 6-18 for the set value). caution to change the value of the duty factor (the value of the cr01n register) during operation, see caution 2 in figure 6-20 ppg output operation timing. remarks 1. for the setting of the to0n pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . in the ppg output oper ation, rectangular wa ves are output from the to0n pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 01n (cr01n) and in 16-bit timer capture/compare register 00n (cr00n), respectively. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 164 figure 6-18. control register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0 crc0n1 crc0n0 0 crc0n cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 7 0 ospt0n 0 ospe0n 0 toc0n4 1 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited). inverts output on match between tm0n and cr01n. disables one-shot pulse output. (d) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) cautions 1. values in the following ra nge should be set in cr00n and cr01n: 0000h cr01n < cr00n ffffh 2. the cycle of the pulse generated through ppg output (cr00n setting value + 1) has a duty of (cr01n setting value + 1)/(cr00n setting value + 1). remark : don?t care n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 165 figure 6-19. configuration diagram of ppg output 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) clear circuit noise eliminator f x f x (f x ) note f x /2 2 (f x /2 4 ) note f x /2 8 (f x /2 6 ) note ti000/p00 (ti001/p05) note 16-bit timer capture/compare register 01n (cr01n) to00/ti010/p01 ( to01/ti011/p06 ) selector output controller note frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 6-20. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm0n count value to0n pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00n capture value cr01n capture value m m n ? 1 n n clear clear cautions 1. cr00n cannot be re written during tm0n operation. 2. in the ppg output operatio n, change the pulse width (rew rite cr01n) during tm0n operation using the following procedure. <1> disable the timer output inversion operati on by match of tm0n and cr01n (toc0n4 = 0) <2> disable the inttm01n interrupt (tmmk01n = 1) <3> rewrite cr01n <4> wait for 1 cycle of the tm0n count clock <5> enable the timer output inversion operati on by match of tm0n and cr01n (toc0n4 = 1) <6> clear the interrupt request flag of inttm01n (tmif01n = 0) <7> enable the inttm01n interrupt (tmmk01n = 0) remarks 1. 0000h m < n ffffh 2. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 166 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00n pin and ti01n pin using 16-bit timer counter 0n (tm0n). there are two measurement methods: measuring with tm0n used in free-running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti00n pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 0n (prm0n) and the valid level of the ti00n or ti01n pin is dete cted twice, thus eliminating noise with a short pulse width. figure 6-21. cr01n capture operat ion with rising edge specified count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figures 6-22 , 6-25 , 6-27 , and 6-29 for the set value). <2> set the count clock by using the prm0n register. <3> set the tmc0n register to start the operation (see figures 6-22 , 6-25 , 6-27 , and 6-29 for the set value). caution to use two capture register s, set the ti00n and ti01n pins. remarks 1. for the setting of the ti00n (or ti01n) pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n (or inttm01n) interrupt, see chapter 17 interrupt functions . 3. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 167 (1) pulse width measurement with free-runni ng counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-ru nning mode, and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. specify both the rising and falling edges by usi ng bits 4 and 5 (es0n0 and es0n1) of prm0n. sampling is performed using the count clock selected by prm0n, and a capture operation is only performed when a valid level of the ti00n pin is detected twic e, thus eliminating noise with a short pulse width. figure 6-22. control register settings for pul se width measurement with free-running counter and one capture register (whe n ti00n and cr01n are used) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 168 figure 6-23. configuration di agram for pulse width measureme nt with free-running counter f x (f x ) note f x /2 2 (f x /2 4 ) note f x /2 8 (f x /2 6 ) note ti00n 16-bit timer counter 0n (tm0n) ovf0n 16-bit timer capture/compare register 01n (cr01n) internal bus inttm01n selector note frequencies without parentheses are for 16-bit timer/ev ent counter 00, and those in parentheses are for 16- bit timer/event counter 01. figure 6-24. timing of pulse width measureme nt operation with free-running counter and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0n count value ti00n pin input cr01n capture value inttm01n ovf0n (d1 ? ? ? chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 169 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free- running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n pin and the ti01n pin. when the edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit time r capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es1n0 and es1n1) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n) and an interrupt request signal (inttm00n) is set. specify both the rising and falling edges as the edges of the ti00n and ti01n pins, by using bits 4 and 5 (es0n0 and es0n1) and bits 6 and 7 (es1n0 and es1n1) of prm0n. sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n or ti01n pin is detected twice, thus eliminating noise with a short pulse width. figure 6-25. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0 crc0n0 1 crc0n cr00n used as capture register captures valid edge of ti01n pin to cr00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 1 es1n0 1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 170 figure 6-26. timing of pulse width measure ment operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01n pin input cr00n capture value inttm01n inttm00n ovf0n (d1 ? ? ? ? chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 171 (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free -running mode, it is possible to measure the pulse width of the signal input to the ti00n pin. when the rising or falling edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bi t timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation is input into cr 01n, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n). sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. figure 6-27. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 172 figure 6-28. timing of pulse width measureme nt operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm01n ovf0n d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t note note clear ovf0n by software. (4) pulse width measurement by means of restart when input of a valid edge to the ti00n pi n is detected, the count value of 16- bit timer counter 0n (tm0n) is taken into 16-bit timer capture/compare register 01n (cr01n), and then the pulse width of t he signal input to the ti00n pin is measured by clearing tm0n and restarting the count operation. either of two edges ? rising or falling ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). sampling is performed using the count clock cycle sele cted by prescaler mode register 0n (prm0n) and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 173 figure 6-29. control register settings for pu lse width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 0 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) figure 6-30. timing of pulse width measurement operation by means of restart (with risi ng edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01n d1 t d2 t d2 d1 d2 d1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 174 6.4.4 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 6-31 for the set value). <2> set the count clock by using the prm0n register. <3> set any value to the cr00n register (0000h cannot be set). <4> set the tmc0n register to start the operation (see figure 6-31 for the set value). remarks 1. for the setting of the ti00n pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . the external event counter counts the num ber of external clock pulses input to the ti00n pin using 16-bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit timer capt ure/compare register 00n (cr00n) value, tm0n is cleared to 0 and the interrupt requ est signal (inttm00n) is generated. input a value other than 0000h to cr00n (a count operation with 1-bit pulse cannot be carried out). any of three edges ? rising, falling, or both edges ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). sampling is performed using the internal clock (f x ) and an operation is only perform ed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 175 figure 6-31. control register setti ngs in external event counter mode (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 1 prm0n0 1 prm0n selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 176 figure 6-32. configuration diagra m of external event counter f x internal bus 16-bit timer capture/compare register 00n (cr00n) match clear ovf0n note noise eliminator 16-bit timer counter 0n (tm0n) valid edge of ti00n inttm00n note ovf0n is set to 1 only when cr00n is set to ffffh. figure 6-33. external event counter oper ation timing (with rising edge specified) ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n ? 1 n 0000h 0001h 0002h 0003h n caution when reading the ext ernal event counter count val ue, tm0n should be read. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 177 6.4.5 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figure 6-34 for the set value). <3> set the toc0n register (see figure 6-34 for the set value). <4> set any value to the cr00n register (0000h cannot be set). <5> set the tmc0n register to start the operation (see figure 6-34 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remarks 1. for the setting of the to0n pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 00n (cr00n). the to0n pin output status is reversed at intervals determined by the count value preset to cr00n + 1 by setting bit 0 (toe0n) and bit 1 (toc0n1) of 16-bit timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. figure 6-34. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 178 figure 6-34. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 0n (toc0n) 7 0 ospt0n 0 ospe0n 0 toc0n4 0 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited). does not invert output on match between tm0n and cr01n. disables one-shot pulse output. (d) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 6-35. square-wave output operation timing count clock tm0n count value cr00n inttm00n to0n pin output 0000h 0001h 0002h n ? 1 n 0000h 0001h 0002h n ? 1 n 0000h n remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 179 6.4.6 one-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti00n pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figures 6-36 and 6-38 for the set value). <3> set the toc0n register (see figures 6-36 and 6-38 for the set value). <4> set any value to the cr00n and cr01n registers (0000h cannot be set). <5> set the tmc0n register to start the operation (see figures 6-36 and 6-38 for the set value). remarks 1. for the setting of the to0n pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n (if necessary, inttm01n) interrupt, see chapter 17 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 6-36, and by setting bit 6 (ospt0n) of the toc0n register to 1 by software. by setting the ospt0n bit to 1, 16-bit timer/event co unter 0n is cleared and starte d, and its output becomes active at the count value (n) set in advance to 16-bit time r capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 00n (cr00n) note . even after the one-shot pulse has been output, the tm0n regi ster continues its operat ion. to stop the tm0n register, the tmc0n3 and tmc0n2 bits of t he tmc0n register must be set to 00. note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. do not set n to m. cautions 1. do not set the ospt0n bit while the one-shot pulse is being outpu t. to output the one-shot pulse again, wait until the current one-s hot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the ti 00n pin or its alternate-function port pin. because the external trigger is valid even in this case, the ti mer is cleared and started even at the level of the ti00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0: chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 180 figure 6-36. control register settings for on e-shot pulse output with software trigger (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 0 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running mode 100 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n as compare register cr01n as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 0 1 1 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. set to 1 for output. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 prm0n prm0n1 prm0n0 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 32 caution do not set 0000h to the cr00n and cr01n registers. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 181 figure 6-37. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1 m ? 1 0001h m + 1 m + 2 0000h count clock tm0n count cr01n set value cr00n set value ospt0n inttm01n inttm00n to0n pin output set tmc0n to 0ch (tm0n count starts) caution 16-bit timer counter 0n st arts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc0n3 and tmc0n2 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 6-38, and by using the valid edge of the ti00n pin as an external trigger. the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00n pin is detected, the 16-bit time r/event counter is clear ed and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (cr00n) note . note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. do not set n to m. caution even if the external trigger is generated again while the one-shot pulse is output, it is ignored. remark n = 0: chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 182 figure 6-38. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 1 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti00n pin. 000 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 01 1 0/1 toc0n lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0 1 prm0n prm0n1 prm0n0 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 00 32 caution do not set the cr00n a nd cr01n registers to 0000h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 183 figure 6-39. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2 m ? 1 0001h 0000h count clock tm0n count value cr01n set value cr00n set value ti00n pin input inttm01n inttm00n to0n pin output when tmc0n is set to 08h (tm0n count starts) t caution 16-bit timer counter 0n st arts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc0n2 and tmc0n3 bits. remark n < m n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 184 6.5 cautions for 16-bit timer/event counters 00 and 01 (1) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 16-bit timer counter 0n (tm0n) is started asynchronously to the count clock. figure 6-40. start timing of 16-bit timer counter 0n (tm0n) tm0n count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/compare re gister setting (in the mode in wh ich clear & start occurs on match between tm0n and cr00n) set 16-bit timer capture/compare registers 00n, 01n (cr 00n, cr01n) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit time r/event counter 0n is used as an event counter. (3) capture register data retention timing the values of 16-bit timer capture/ compare registers 00n and 01n (cr00n and cr01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. (4) valid edge setting set the valid edge of the ti00n pin after setting bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n (tmc0n) to 0, 0, respectively, and then sto pping timer operation. the valid edge is set using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). (5) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt0n bit to 1. do not output the one-shot pulse again until inttm00n, which occurs upon a match with the cr00n register, or inttm01n, which occurs upon a match with the cr01n register, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of 16-bit timer/ev ent counter 0n with a software trigger, do not change the level of the ti00n pin or its alternate function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti00n pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0: chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 185 (6) operation of ovf0n flag <1> the ofv0n flag is also set to 1 in the following case. when of the following modes: the mode in which cl ear & start occurs on a match between tm0n and cr00n, the mode in which clear & start occurs on a ti 0n valid edge, or the free-running mode, is selected chapter 6 16-bit timer/event counters 00 and 01 user?s manual u16228ej2v0ud 186 (8) timer operation <1> even if 16-bit timer counter 0n (tm0n) is read, t he value is not captured by 16-bit timer capture/compare register 01n (cr01n). <2> regardless of the cpu?s operation mode, when the timer stops, the input signals to the ti00n/ti01n pins are not acknowledged. <3> the one-shot pulse output mode oper ates correctly only in the free-ru nning mode and the mode in which clear & start occurs at the ti00n vali d edge. in the mode in which clear & start occurs on a match between the tm0n register and cr00n register, one-shot pulse output is not possi ble because an overflow does not occur. (9) capture operation <1> if ti00n valid edge is specified as the count clock, a capture operation by the capt ure register specified as the trigger for ti00n is not possible. <2> to ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 0n (prm0n). <3> the capture operation is performed at the falling edge of the count clock. an interrupt request input (inttm00n/inttm01n), however, is generated at the rise of the next count clock. (10) compare operation a capture operation may not be performed for cr00n/cr01n se t in compare mode even if a capture trigger has been input. (11) edge detection <1> if the ti00n or ti01n pin is high level immediately a fter system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti 00n or ti01n pin to enable the 16-bit timer counter 0n (tm0n) operation, a rising edge is detected immediately after the operation is enabled. be careful therefore when pulling up the ti00n or ti01n pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to remove noise differs w hen the ti00n valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 0n (prm0n). the capture operation is started only after a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 user?s manual u16228ej2v0ud 187 chapter 7 8-bit timer/even t counters 50 and 51 7.1 functions of 8-bit ti mer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? ? ? ? chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 188 figure 7-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/p33/intp4 f x /2 8 f x /2 12 f x f x /2 match mask circuit ovf clear 3 selector tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p33/intp4 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector output latch (p33) pm33 f x /2 6 f x /2 4 notes 1. timer output f/f 2. pwm output f/f chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 189 7.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. table 7-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) or port mode register 3 (pm3) port register 1 (p1) or port register 3 (p3) (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 7-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n. chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 190 (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in pwm mode, when the to5n pin becomes active due to a tm5n overflow and the values of tm5n and cr5n match, the to5n pin becomes inactive. the value of cr5n can be set within 00h to ffh. reset input clears cr5n to 00h. figure 7-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in which clear & start oc curs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite peri od 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 191 7.3 registers controlling 8-bit ti mer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 1 (pm1) or port mode register 3 (pm3) ? port register 1 (p1) or port register 3 (p3) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit time r/event counter 5n and the valid edge of ti5n input. tcl5n can be set by an 8-bit memory manipulation instruction. reset input clears tcl5n to 00h. remark n = 0, 1 figure 7-5. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 0 1 0 f x (10 mhz) 0 1 1 f x /2 (5 mhz) 1 0 0 f x /2 2 (2.5 mhz) 1 0 1 f x /2 6 (156.25 khz) 1 1 0 f x /2 8 (39.06 khz) 1 1 1 f x /2 13 (1.22 khz) cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ring-osc clock, the operation of 8-bit ti mer/event counter 50 is not guaranteed. 2. when rewriting tcl50 to other da ta, stop the timer operation beforehand. 3. be sure to set bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz. chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 192 figure 7-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 0 1 0 f x (10 mhz) 0 1 1 f x /2 (5 mhz) 1 0 0 f x /2 4 (625 khz) 1 0 1 f x /2 6 (156.25 khz) 1 1 0 f x /2 8 (39.06 khz) 1 1 1 f x /2 12 (2.44 khz) cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ring- osc clock, the operation of 8-bit ti mer/event counter 51 is not guaranteed. 2. when rewriting tcl51 to other da ta, stop the timer operation beforehand. 3. be sure to set bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz. chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 193 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0, 1 figure 7-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (tm50 output is low level) 1 output enabled note bits 2 and 3 are write-only. (refer to cautions and remarks on the next page.) chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 194 figure 7-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (tm51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. do not rewrite following bits simultaneously. ? ? ? ? ? chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 195 (3) port mode registers 1 and 3 (pm1, pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p 33/to51/ti51/intp4 pins for timer output, clear pm17 and pm33 and the output latches of p17 and p33 to 0. when using the p17/to50/ti50 and p33/ to51/ti51/intp4 pins for timer input, set pm17 and pm33 to 1. the output latches of p17 and p33 at this time may be 0 or 1. pm1 and pm3 can be set by a 1-bit or 8- bit memory manipulation instruction. reset input sets these registers to ffh. figure 7-9. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 7-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 0 0 0 0 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 196 7.4 operations of 8-bit timer/event counters 50 and 51 7.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat generates interrupt reques ts repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? ? ? chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 197 figure 7-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 198 7.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to ti5n by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection regist er 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? ? ? ? chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 199 7.4.3 square-wave output operation a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n ) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, sele ct the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f inversion enabled timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 caution do not write other values to cr5n during operation. remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 200 figure 7-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output c an be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 7.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 201 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 pwm output operation <1> pwm output (output from to5n) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is outpu t. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 7-14 and 7-15 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 202 figure 7-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> <3> inactive level active level <5> t (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n to5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 l t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level t remarks 1. <1> to <3> and <5> in figure 7-14 (a) correspond to <1> to <3> and <5> in pwm output operation in 7.4.4 (1) pwm output basic operation . 2. n = 0, 1 chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 203 (2) operation with cr5n changed figure 7-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n betw een <1> and <2> in figure 7-15, the value read differs from the actual value (read value: m, actual value of cr5n: n). chapter 7 8-bit timer/event counters 50 and 51 user?s manual u16228ej2v0ud 204 7.5 cautions for 8-bit ti mer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm 51) are started asynchronous ly to the count clock. figure 7-16. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1 user?s manual u16228ej2v0ud 205 chapter 8 8-bit timers h0 and h1 8.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? interval timer ? pwm output mode ? square-wave output ? carrier generator mode (8-bit timer h1 only) 8.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 include the following hardware. table 8-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output tohn control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note port mode register 1 (pm1) port register 1 (p1) note 8-bit timer h1 only remark n = 0, 1 figures 8-1 and 8-2 show the block diagrams. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 206 figure 8-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p15 inttmh0 f x f x /2 f x /2 2 f x /2 6 f x /2 10 1 0 f/f r 3 2 pm15 match internal bus 8-bit timer h mode control register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p15) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 207 figure 8-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 interrupt generator output controller level inversion pm16 output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode control register 1 (tmhmd1) selector chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 208 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 8-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritte n during timer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 8-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 cmp1n can be rewritten during timer count operation. an interrupt request signal (inttmhn) is generated if the values of the timer counter and cmp1n match after setting cmp1n in carrier generator mode. the timer counter va lue is cleared at the same time. if the cmp1n value is rewritten during timer operation, transferring is performed at the timing at which the counter value and cmp1n value match. if the transfer timing and writing from cpu to cmp1n conflict, transfer is not performed. caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the ti mer count operation was stopped (tmhen = 0) (be sure to set again even if se tting the same value to cmp1n). remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 209 8.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 1 (pm1) ? port register 1 (p1) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 210 figure 8-5. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f x f x /2 f x /2 2 f x /2 6 f x /2 10 tm50 output note cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 (10 mhz) (5 mhz) (2.5 mhz) (156.25 khz) (9.77 khz) count clock (f cnt ) selection setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> note to select the tm50 output as a count clock, start operation by setting 8-bit timer/event counter 50 in the pwm output mode (bit 6 (tmc506) of the tmc50 regist er = 1), and then set cks02, cks01, and cks00 to 1, 0, and 1, respectively. set the high/low level width of the count clock so that the specifications of the input width of ti50 are satisfied (see ac characteristics (1) basic operation in chapter 29 to chapter 31 ). it is not necessary to enable the to50 pin as a timer output pin (bit 0 (toe50) of the tmc register may be 0 or 1). chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 211 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit timer h0 is not guaranteed. 2. when tmhe0 = 1, setting the other bits of the tmhmd0 register is prohibited. 3. in the pwm output mode, be sure to set 8- bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same val ue to the cmp10 register). remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 212 figure 8-6. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock (f cnt ) selection setting prohibited other than above interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 tmmd10 0 1 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit timer h1 is not guaranteed (except when cks12, cks11, cks10 = 1, 0, 1 (f r /2 7 )). 2. when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. 3. in the pwm output mode and carrier genera tor mode, be sure to set 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmh e1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 4. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 213 remarks 1. f x : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency 3. figures in parentheses apply to operation at f x = 10 mhz, f r = 240 khz (typ.). (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 8-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note low-level output high-level output low-level output carrier pulse output rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p15/toh0 and p16/toh1/intp5 pins for timer output, clear pm15 and pm16 and the output latches of p15 and p16 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 8-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 214 8.4 operation of 8-bit timers h0 and h1 8.4.1 operation as inter val timer/square-wave output when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 8-9. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ? compare value (n) <2> count operation starts when tmhen = 1. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval time = (n +1)/f cnt <4> subsequently, the inttmhn signal is generated at the same interval. to stop the count operation, clear tmhen to 0. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 215 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 8-10. timing of interval time r/square-wave output operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by clearing the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 01h to feh chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 216 figure 8-10. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 217 8.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n ) controls the cycle of timer output (t ohn). rewriting the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the dut y of timer output (tohn). re writing the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 8-11. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare register that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0 n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, a nd tohn output becomes active. at the same time, the compare register to be compared with 8-bit timer c ounter hn is changed from the cmp0n register to the cmp1n register. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 218 <4> when 8-bit timer counter hn and the cmp1n regist er match, tohn output bec omes inactive and the compare register to be compared with 8-bit timer coun ter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode , three operation clocks (signal sel ected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 219 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0 n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh remark n = 0, 1 figure 8-12. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains inactive (when tolevn = 0). <2> when the values of 8-bit timer counter hn and the cmp0 n register match, the tohn output level is inverted, the value of 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of 8-bit timer counter hn and the cm p1n register match, the le vel of the tohn output is returned. at this time, the 8-bit timer counter val ue is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operati on makes the inttmhn signal and tohn output inactive. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 220 figure 8-12. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 221 figure 8-12. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 222 figure 8-12. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 01h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp1n 01h a5h 03h 01h (03h) <1> <3> <4> <2> <2>' <5> <6> <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, the tohn output remains inactive (when tolevn = 0). <2> the cmp1n register value can be changed during time r counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output becomes active, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter hn and the cmp1n register before the change match, the value is transferred to the cmp1n register and the cmp1n re gister value is changed (<2>?). however, three count clocks or more are required fr om when the cmp1n register value is changed to when the value is transferred to the register. if a match si gnal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cm p1n register after the change match, the tohn output becomes inactive. 8-bit timer counter hn is no t cleared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operati on makes the inttmhn signal and tohn output inactive. remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 223 8.4.3 carrier generator mode operation (8-bit timer h1 only) the carrier clock generated by 8-bit timer h1 is output in the cycle set by 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is out put from the toh1 output. (1) carrier generation in carrier generator mode, 8-bit timer h compare regist er 01 (cmp01) generates a low-level width carrier pulse waveform and 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during 8-bit timer h1 operat ion is possible but rewriting the cmp01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request sig nal (inttm51) of 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier co ntrol register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 224 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrzb1 bit to the nrz1 bit is as shown below. figure 8-13. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <1> the inttm51 signal is synchronized with the count cl ock of 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is transferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. cautions 1. do not rewrite the nrzb1 bit again until at least the second clock afte r it has been rewritten, or else the transfer from the nrzb1 bi t to the nrz1 bit is not guaranteed. 2. when 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 225 (3) usage outputs an arbitrary carrier clock from the toh1 pin. <1> set each register. figure 8-14. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled timer output level inversion setting carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 0/1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? ? ? ? ? chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 226 if the setting value of the cmp01 register is n, the setting value of the cmp 11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high-level width : carrier clock ou tput width = ( m + 1) : (n + m + 2) cautions 1. be sure to set the cm p11 register when starting the time r count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set agai n even if setting the same value to the cmp11 register). 2. set so that the count cloc k frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. (4) timing chart the carrier output control timing is shown below. cautions 1. set the values of the cmp01 and cmp11 registers in a range of 01h to ffh. 2. in the carrier generator mode, three ope rating clocks (signal selected by cks12 to cks10 bits of tmhmd1 register) or more are requi red from when the cmp11 register value is changed to when the value is transferred to the register. 3. be sure to set the rmc1 bit be fore the count operation is started. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 227 figure 8-15. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n 00h n 00h n 00h n 00h n 00h n 00h n n n 0 0 1 1 0 0 1 1 0 0 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l cmpn0 cmpn1 tmhen inttmhn carrier clock 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn inttm5n nrzbn nrzn carrier clock inttm5hn 8-bit timer hn count clock 8-bit timer counter hn count value <1> <2> <3> <4> <5> <6> <7> <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a c ount operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer sign al for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level. chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 228 figure 8-15. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n l 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m 0 0 1 1 0 0 1 1 0 0 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l cmpn0 cmpn1 tmhen inttmhn carrier clock 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn inttm5n nrzbn nrzn carrier clock inttm5hn 8-bit timer hn count clock 8-bit timer counter hn count value <1> <2> <3> <4> <5> <6> <7> <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a c ount operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). chapter 8 8-bit timers h0 and h1 user?s manual u16228ej2v0ud 229 figure 8-15. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, 8-bit timer h1 starts a count oper ation. at that time, the carrier clock is held at the inactive level. <2> when the count value of 8-bit timer counter h1 matche s the cmp01 register value, 8-bit timer counter h1 is cleared and the inttmh1 signal is output. <3> the cmp11 register can be rewritten during 8-bit timer h1 operation, however, the changed value (l) is latched. the cmp11 register is changed when the co unt value of 8-bit timer counter h1 and the cmp11 register value before t he change (m) match (<3>?). <4> when the count value of 8-bit timer counter h1 and the cmp11 register value before the change (m) match, the inttmh1 signal is output, the carrier signal is inve rted, and 8-bit timer counter h1 is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter h1 and the cmp11 register value match again is indicated by the value after the change (l). user?s manual u16228ej2v0ud 230 chapter 9 watch timer 9.1 functions of watch timer the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 9-1 shows the watch timer block diagram. figure 9-1. block diagram of watch timer f x /2 7 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 f w clear 11-bit prescaler clear 5-bit counter watch timer operation mode register (wtm) internal bus selector selector selector selector f wx /2 4 f wx /2 5 f wx remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency f wx : f w or f w /2 9 chapter 9 watch timer user?s manual u16228ej2v0ud 231 (1) watch timer when the x1 input clock or subsystem clock is used, interrupt reques ts (intwt) are gener ated at preset intervals. table 9-1. watch timer interrupt time interrupt time when operated at f xt = 32.768 khz when operated at f x = 10 mhz 2 4 /f w 488 s 205 s 2 5 /f w 977 s 410 s 2 13 /f w 0.25 s 0.105 s 2 14 /f w 0.5 s 0.210 s remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (2) interval timer interrupt requests (intwti) are gen erated at preset time intervals. table 9-2. interval timer interval time interval time when operated at f xt = 32.768 khz when operated at f x = 10 mhz 2 4 /f w 488 s 205 s 2 5 /f w 977 s 410 s 2 6 /f w 1.95 ms 820 s 2 7 /f w 3.91 ms 1.64 ms 2 8 /f w 7.81 ms 3.28 ms 2 9 /f w 15.6 ms 6.55 ms 2 10 /f w 31.3 ms 13.1 ms 2 11 /f w 62.5 ms 26.2 ms remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency chapter 9 watch timer user?s manual u16228ej2v0ud 232 9.2 configuration of watch timer the watch timer includes the following hardware. table 9-3. watch timer configuration item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) 9.3 register controlling watch timer the watch timer is controlled by the wa tch timer operation mode register (wtm). ? watch timer operation mode register (wtm) this register sets the watch timer count clock, enabl es/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. chapter 9 watch timer user?s manual u16228ej2v0ud 233 figure 9-2. format of watch timer operation mode register (wtm) address: ff6fh after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm7 watch timer count clock selection 0 f x /2 7 (78.125 khz) 1 f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 9 /f w 1 1 0 2 10 /f w 1 1 1 2 11 /f w wtm3 wtm2 interrupt time selection 0 0 2 14 /f w 0 1 2 13 /f w 1 0 2 5 /f w 1 1 2 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear both prescaler and timer) 1 operation enable caution do not change the count clock and interval ti me (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : x1 input clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f x = 10 mhz, f xt = 32.768 khz. chapter 9 watch timer user?s manual u16228ej2v0ud 234 9.4 watch timer operations 9.4.1 watch timer operation the watch timer generates an interrupt r equest (intwt) at a specific time interval by using the x1 input clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer oper ation mode register (wtm) are set to 1, the count operation starts. when these bits are set to 0, the 5-bit counter is cleared and the count operation stops. when the interval timer is simultaneously operated, zero-s econd start can be achieved only for the watch timer by setting wtm1 to 0. in this case, however, the 11-bit pr escaler is not cleared. therefore, an error up to 2 11 1/f w seconds occurs in the first overfl ow (intwt) after zero-second start. the interrupt request is generated at the following time intervals. table 9-4. watch timer interrupt time wtm3 wtm2 interrupt time selection when operated at f xt = 32.768 khz (wtm7 = 1) when operated at f x = 10 mhz (wtm7 = 0) 0 0 2 14 /f w 0.5 s 0.210 s 0 1 2 13 /f w 0.25 s 0.105 s 1 0 2 5 /f w 977 s 410 s 1 1 2 4 /f w 488 s 205 s remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency chapter 9 watch timer user?s manual u16228ej2v0ud 235 9.4.2 interval timer operation the watch timer operates as interval timer which generates in terrupt requests (intwti) r epeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm 4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count operation starts. when this bit is set to 0, the count operation stops. table 9-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f xt = 32.768 khz (wtm7 = 1) when operated at f x = 10 mhz (wtm7 = 0) 0 0 0 2 4 /f w 488 s 205 s 0 0 1 2 5 /f w 977 s 410 s 0 1 0 2 6 /f w 1.95 ms 820 s 0 1 1 2 7 /f w 3.91 ms 1.64 ms 1 0 0 2 8 /f w 7.81 ms 3.28 ms 1 0 1 2 9 /f w 15.6 ms 6.55 ms 1 1 0 2 10 /f w 31.3 ms 13.1 ms 1 1 1 2 11 /f w 62.5 ms 26.2 ms remark f x : x1 input clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency figure 9-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) n t n t remark f w : watch timer clock frequency n: the number of times of interval timer operations figures in parentheses are for operation with f w = 32.768 khz (wtm7 = 1, wtm3, wtm2 = 0, 0) chapter 9 watch timer user?s manual u16228ej2v0ud 236 9.5 cautions for watch timer when operation of the watch timer and 5- bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the inte rval until the first interr upt request (intwt) is generated after the register is set does not exactly match the specif ication made with bit 3 (wtm3) of wtm. this is because there is a delay of one 11-bit prescaler output cycle until th e 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. figure 9-4. example of generation of watch timer inte rrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt user?s manual u16228ej2v0ud 237 chapter 10 watchdog timer 10.1 functions of watchdog timer the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, refer to chapter 20 reset function . table 10-1. loop detection time of watchdog timer loop detection time during ring-osc clock o peration during x1 input clock operation f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz the operation mode of the watchdog time r (wdt) is switched according to t he mask option setting of the on-chip ring-osc as shown in table 10-2. chapter 10 watchdog timer user?s manual u16228ej2v0ud 238 table 10-2. mask option setting an d watchdog timer operation mode mask option ring-osc cannot be stopped ring-osc can be stopped by software watchdog timer clock source fixed to f r note 1 . ? ? ? ? ? ? ? chapter 10 watchdog timer user?s manual u16228ej2v0ud 239 10.2 configuration of watchdog timer the watchdog timer includes following hardware. table 10-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) figure 10-1. block diag ram of watchdog timer f r /2 2 clock input controller output controller internal reset signal wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter or f xp /2 13 to f xp /2 20 f r /2 11 to f r /2 18 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 3 2 clear mask option (to set ?ring-osc cannot be stopped? or ?ring-osc can be stopped by software?) chapter 10 watchdog timer user?s manual u16228ej2v0ud 240 10.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipula tion instruction and can be read many times, but can be written only once after reset is released. reset input sets this register to 67h. figure 10-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff98h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 ring-osc clock (f r ) 0 1 x1 input clock (f xp ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during ring-osc clock operation during x1 input clock operation 0 0 0 f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) 0 0 1 f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) 0 1 0 f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) 0 1 1 f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) 1 0 0 f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) 1 0 1 f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) 1 1 0 f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) 1 1 1 f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) notes 1. if ?ring-osc cannot be stopped? is specified by a mask option, this cannot be set. the ring- osc clock will be selected no matter what value is written. 2. reset is released at the maximu m cycle (wdcs2, 1, 0 = 1, 1, 1). chapter 10 watchdog timer user?s manual u16228ej2v0ud 241 cautions 1. if data is written to wdtm, a wait cycle is generate d. do not write data to wdtm when the cpu is operating on the subsyst em clock and the x1 input clock is stopped. for details, see chap ter 34 cautions for wait. 2. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?ring-osc cannot be stopped? is selected by a mask option, other values are ignored). 3. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing atte mpted a second time, an internal reset signal is generated. 4. wdtm cannot be set by a 1-bi t memory manipulation instruction. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. : don?t care 4. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 9ah. figure 10-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. 2. if a 1-bit memory manipulation instruct ion is executed for wdte, an internal reset signal is generated. 3. the value read from wd te is 9ah (this differs from the written value (ach)). chapter 10 watchdog timer user?s manual u16228ej2v0ud 242 10.4 operation of watchdog timer 10.4.1 watchdog timer operation when ?ring-osc can not be stopped? is selected by a mask option the operation clock of watchdog timer is fixed to the ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) . the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: ring-osc clock ? cycle: f r /2 18 (1.09 seconds: at operation with f r = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2 . ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are exec uted, writing ach to wdte clears the count to 0, enabling recounting. notes 1. the operation clock (ring-osc clock) cannot be ch anged. if any value is written to bits 3 and 4 (wdcs3, wdcs4) of wdtm, it is ignored. 2. as soon as wdtm is written, the c ounter of the watchdog timer is cleared. caution in this mode, operation of the watchdog timer absolutely cannot be stopped even during stop instruction execution. for 8-bit timer h1 (tmh1), a division of the ring-osc can be selected as the count source, so clear the wa tchdog timer using the interrupt request of tmh1 before the watchdog timer overflows after stop instruction execution. if this processing is not performed, an internal reset signal is generated when th e watchdog timer overflows after stop instruction execution. chapter 10 watchdog timer user?s manual u16228ej2v0ud 243 10.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option the operation clock of the watchdog timer can be selected as either the ring-osc clock or the x1 input clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? ? ? ? ? ? ? ? chapter 10 watchdog timer user?s manual u16228ej2v0ud 244 10.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during stop instruction execution regardless of whether the x1 input clock or ring-osc clock is being used. (1) when the cpu clock and the watchdog time r operation clock are the x1 input clock (f xp ) when the stop instruction is executed when stop instruction is executed, o peration of the watchdog timer is stopp ed. after stop mode is released, counting stops for the oscillation stabiliz ation time set by the oscillation stab ilization time select register (osts) and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 10-4. operation in stop mode (cpu cl ock and wdt operation clock: x1 input clock) watchdog timer operating operation stopped operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) (2) when the cpu clock is the x1 input clock (f xp ) and the watchdog timer operati on clock is the ring-osc clock (f r ) when the stop instruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 10-5. operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) operating operation stopped chapter 10 watchdog timer user?s manual u16228ej2v0ud 245 (3) when the cpu clock is the ring-osc clock (f r ) and the watchdog timer operati on clock is the x1 input clock (f xp ) when the stop inst ruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier , and then counting is started using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. <1> the oscillation stabilization time set by the oscillat ion stabilization time select register (osts) elapses. <2> the cpu clock is switched to the x1 input clock (f xp ). figure 10-6. operation in stop mode (cpu clock: ring-osc clock, wdt op eration clock: x1 input clock) <1> timing when counting is started afte r the oscillation stabilization time set by the oscillation stabilization time select register (osts) has elapsed watchdog timer operating operation stopped operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) <2> timing when counting is started after the cp u clock is switched to the x1 input clock (f xp ) operating operation stopped operating f r f xp f r f xp note cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) normal operation (x1 input clock) cpu clock oscillation stopped stop oscillation stabilization time (set by osts register) watchdog timer note confirm the oscillation stabilization time of f xp using the oscillation stabilization time counter status register (ostc). chapter 10 watchdog timer user?s manual u16228ej2v0ud 246 (4) when cpu clock and watchdog timer ope ration clock are the ring-osc clocks (f r ) during stop instruction execution when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 10-7. operation in stop mode (cpu clo ck and wdt operation clo ck: ring-osc clock) watchdog timer operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) operating operation stopped 10.4.4 watchdog timer operation in halt mode (when ?r ing-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during halt instruction execution regardle ss of whether the cpu clock is the x1 input clock (f xp ), ring-osc clock (f r ), or subsystem clock (f xt ), or whether the operation clock of the watchdog timer is the x1 input clock (f xp ) or ring-osc clock (f r ). after halt mode is released, counting is started again using the operation clock before the operation was st opped. at this time, the counter is not cleared to 0 but holds its value. figure 10-8. operation in halt mode watchdog timer operating f r f xp cpu operation normal operation operating halt operation stopped f xt normal operation user?s manual u16228ej2v0ud 247 chapter 11 clock output/buzzer output controller 11.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 11-1 shows the block diagram of clock output/buzzer output controller. figure 11-1. block diagram of clo ck output/buzzer output controller f x f x /2 10 to f x /2 13 f x to f x /2 7 f xt bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/intp6/p140 buz/busy0/ intp7/p141 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p141) pm141 output latch (p140) pm140 selector selector chapter 11 clock output/buzzer output controller user?s manual u16228ej2v0ud 248 11.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 11-1. clock output/buzzer output controller configuration item configuration control registers clock output selection register (cks) port mode register 14 (pm14) port register 14 (p14) 11.3 register controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 14 (pm14) (1) clock output selection register (cks) this register sets output enable/disable for clock out put (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears cks to 00h. chapter 11 clock output/buzzer output controller user?s manual u16228ej2v0ud 249 figure 11-2. format of clock out put selection register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. bcs1 bcs0 buz output clock selection 0 0 f x /2 10 (9.77 khz) 0 1 f x /2 11 (4.88 khz) 1 0 f x /2 12 (2.44 khz) 1 1 f x /2 13 (1.22 khz) cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0 0 0 0 f x (10 mhz) 0 0 0 1 f x /2 (5 mhz) 0 0 1 0 f x /2 2 (2.5 mhz) 0 0 1 1 f x /2 3 (1.25 mhz) 0 1 0 0 f x /2 4 (625 khz) 0 1 0 1 f x /2 5 (312.5 khz) 0 1 1 0 f x /2 6 (156.25 khz) 0 1 1 1 f x /2 7 (78.125 khz) 1 0 0 0 f xt (32.768 khz) other than above setting prohibited remarks 1. f x : x1 input clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f x = 10 mhz or f xt = 32.768 khz. chapter 11 clock output/buzzer output controller user?s manual u16228ej2v0ud 250 (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pcl pin for clock output and the p141/intp7/buz pin for buzzer output, set pm140, pm141 and the output latch of p140, p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm14 to ffh. figure 11-3. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 1 1 1 1 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off) 11.4 clock output/buzzer output controller operations 11.4.1 clock output operation the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as show n in figure 11-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing high level of the clock. figure 11-4. remote control output application example cloe clock output ** 11.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output. user?s manual u16228ej2v0ud 251 chapter 12 a/d converter 12.1 functions of a/d converter the a/d converter converts an analog input signal into a digi tal value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following two functions. (1) 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani7. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. (2) power-fail de tection function this function is used to detect a voltage drop in a batte ry. the a/d conversion result (adcr register value) and power-fail comparison threshold register (pft) va lue are compared. intad is generated only when a comparative condition has been matched. figure 12-1. block diag ram of a/d converter av ref av ss intad adcs bit 3 ads2 ads1 ads0 adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator controller a/d conversion result register (adcr) power-fail comparison threshold register (pft) analog input channel specification register (ads) a/d converter mode register (adm) pfen pfcm power-fail comparison mode register (pfm) internal bus comparator ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 successive approximation register (sar) selector tap selector chapter 12 a/d converter user?s manual u16228ej2v0ud 252 12.2 configuration of a/d converter the a/d converter includes the following hardware. table 12-1. registers of a/ d converter used on software item configuration registers successive approximat ion register (sar) a/d conversion result register (adcr) a/d converter mode register (adm) analog input channel specification register (ads) power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) (1) ani0 to ani7 pins these are the analog input pins of the 8- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin by the analog input channel specification register (ads) can be used as input port pins. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled anal og input voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the analog input signal. (4) voltage comparator the voltage comparator compar es the sampled analog input voltage and t he output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) a/d conversion result register (adcr) the result of a/d conversion is loa ded from the successive approximation register (sar) to this register each time a/d conversion is completed, and the adcr register hol ds the result of a/d conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) controller when a/d conversion has been completed or when the powe r-fail detection function is used, this controller compares the result of a/d conversi on (value of the adcr register) and t he value of the power-fail comparison threshold register (pft). it generates the interrupt intad onl y if a specified comparison condition is satisfied as a result. chapter 12 a/d converter user?s manual u16228ej2v0ud 253 (8) av ref pin this pin inputs an analog power/reference voltage to the a/ d converter. always use this pin at the same potential as that of the v dd pin even when the a/d converter is not used. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . in the standby mode, the current flowi ng through the series resistor string can be reduced by lowering the voltage input to the av ref pin to the av ss level. (9) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (10) a/d converter mode register (adm) this register is used to set the conversion time of the analog input signal to be conver ted, and to start or stop the conversion operation. (11) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) power-fail comparis on mode register (pfm) this register is used to set the power-fail monitor mode. (13) power-fail comparison threshold register (pft) this register is used to set the threshold value that is to be compared with the value of the a/d conversion result register (adcr). chapter 12 a/d converter user?s manual u16228ej2v0ud 254 12.3 registers used in a/d converter the a/d converter uses the following five registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? a/d conversion result register (adcr) ? power-fail comparison mode register (pfm) ? power-fail comparison threshold register (pft) (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-2. format of a/d converter mode register (adm) 144 s 120 s 96 s 72 s 60 s 48 s adce 0 0 fr0 fr1 fr2 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 conversion time selection note 1 288/f x 240/f x 192/f x 144/f x 120/f x 96/f x setting prohibited fr2 0 0 0 1 1 1 other than above fr1 0 0 1 0 0 1 fr0 0 1 0 0 1 0 <0> 1 2 3 4 5 6 <7> adm address: ff28h after reset: 00h r/w symbol 34.3 s 28.6 s 22.9 s 17.2 s 14.3 s 11.5 s 28.8 s 24.0 s 19.2 s 14.4 s 12.0 s 9.6 s f x = 8.38 mhz f x = 10 mhz boost reference voltage generator operation control note 2 stops operation of reference voltage generator enables operation of reference voltage generator adce 0 1 f x = 2 mhz chapter 12 a/d converter user?s manual u16228ej2v0ud 255 notes 1. set so that the a/d conver sion time is as follows. ? standard products, (a) grade products: 14 s or longer but less than 100 s ? (a1) grade products: 14 s or longer but less than 60 s ? (a2) grade products: 16 s or longer but less than 48 s 2. a booster circuit is incorporated to realize low-vo ltage operation. the operation of the circuit that generates the reference voltage for boosting is controlled by adce, and it takes 14 s from operation start to operation stabilization. theref ore, when adcs is set to 1 after 14 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. remark f x : x1 input clock oscillation frequency table 12-2. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 12-3. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note the time from the rising of the adce bi t to the falling of the adcs bit must be 14 s or longer to stabilize the reference voltage. cautions 1. a/d conversion must be stopped before re writing bits fr0 to fr2 to values other than the identical data. 2. for the sampling time of th e a/d converter and the a/d con version start delay time, see (11) in 12.6 cautions for a/d converter. 3. if data is written to adm, a wait cycle is generated. do not write data to adm when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, see chapter 34 cautions for wait. remark f x : x1 input clock oscillation frequency chapter 12 a/d converter user?s manual u16228ej2v0ud 256 (2) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-4. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to clea r bits 3 to 7 of ads to 0. 2. if data is written to ads, a wait cycle is gene rated. do not write data to ads when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, see chapter 34 cautions for wait. chapter 12 a/d converter user?s manual u16228ej2v0ud 257 (3) a/d conversion result register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower six bits are fixed to 0. each time a/d conversion ends, the conversion resu lt is loaded from the successive appr oximation register, and is stored in adcr in order starting from the most significant bit (msb) . ff09h indicates the higher 8 bits of the conversion result, and ff08h indicates the lower 2 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset input makes adcr undefined. figure 12-5. format of a/d con version result register (adcr) symbol address: ff08h, ff09h after reset: undefined r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may b ecome undefined. read the conversion result following con version completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is ge nerated. do not read data from adcr when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 34 cautions for wait. chapter 12 a/d converter user?s manual u16228ej2v0ud 258 (4) power-fail comparison mode register (pfm) the power-fail comparison mode regist er (pfm) is used to compare the a/ d conversion result (value of the adcr register) and the value of the power-f ail comparison threshold register (pft). pfm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-6. format of power-fail comparison mode register (pfm) 0 0 0 0 0 0 pfcm pfen power-fail comparison enable stops power-fail comparison (used as a normal a/d converter) enables power-fail comparison (used for power-fail detection) pfen 0 1 power-fail comparison mode selection interrupt request signal (intad) generation no intad generation intad generation no intad generation higher 8 bits of adcr pft higher 8 bits of adcr < pft higher 8 bits of adcr pft higher 8 bits of adcr < pft pfcm 0 1 0 1 2 3 4 5 <6> <7> pfm address: ff2ah after reset: 00h r/w symbol caution if data is written to pfm, a wait cycle is ge nerated. do not write data to pfm when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, see chapter 34 cautions for wait. (5) power-fail comparison th reshold register (pft) the power-fail comparison threshold register (pft) is a r egister that sets the threshold value when comparing the values with the a/d conversion result. 8-bit data in pft is compared to the higher 8 bi ts (ff09h) of the 10-bit a/d conversion result. pft can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-7. format of power-fail comparison threshold register (pft) pft0 pft1 pft2 pft3 pft4 pft5 pft6 pft7 0 1 2 3 4 5 6 7 pft address: ff2bh after reset: 00h r/w symbol caution if data is written to pft, a wait cycle is generated. do not write data to pft when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, see chapter 34 cautions for wait. chapter 12 a/d converter user?s manual u16228ej2v0ud 259 12.4 a/d converter operations 12.4.1 basic operations of a/d converter <1> select one channel for a/d conversion using the analog input channel specification register (ads). <2> set adce to 1 and wait for 14 s or longer. <3> set adcs to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <5> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation has ended. <6> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <7> the voltage difference between the se ries resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <8> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and analog input vo ltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <9> comparison is continued in this way up to bit 0 of sar. <10> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion result register (adcr) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <11> repeat steps <4> to <10>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <3>. to restart a/d conversion from the status of adce = 0, however, start from <2>. chapter 12 a/d converter user?s manual u16228ej2v0ud 260 figure 12-8. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to one of the adm, analog input channel specif ication register (ads), power-fail comparison mode register (pfm), or power-fail comparison threshold regist er (pft) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset input makes the a/d conversion re sult register (adcr) undefined. chapter 12 a/d converter user?s manual u16228ej2v0ud 261 12.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the a/d conversion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or (adcr ? 0.5) v ain < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 12-9 shows the relationship between the ana log input voltage and the a/d conversion result. figure 12-9. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result (adcr) sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 chapter 12 a/d converter user?s manual u16228ej2v0ud 262 12.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. in addition, the following two functions can be selected by setting of bit 7 (pfen) of the power-fail comparison mode register (pfm). ? normal 10-bit a/d converter (pfen = 0) ? power-fail detection function (pfen = 1) (1) a/d conversion operation (when pfen = 0) by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 0, t he a/d conversion operation of the volt age, which is applied to the analog input pin specified by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/ d conversion has started and when one a/d conversion has been completed, the next a/ d conversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if adm, ads, the power-fail comparison mode register (p fm), and the power-fail comparison threshold register (pft) are rewritten during a/d conversion, the a/d conversion operation under execution is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result is undefined. figure 12-10. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr intad (pfen = 0) conversion is stopped conversion result is not retained remarks 1. n = 0 to 7 2. m = 0 to 7 chapter 12 a/d converter user?s manual u16228ej2v0ud 263 (2) power-fail detection f unction (when pfen = 1) by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 1, the a/d conversion operation of the vo ltage applied to the analog input pin specified by the analog input channel spec ification register (ads) is started. when the a/d conversion has been completed, the result of the a/d conversion is st ored in the a/d conversion result register (adcr), the values are compared with power-fail comparison threshold register (pft), and an interrupt request signal (intad) is generated under the condition specified by bit 6 (pfcm) of pfm. <1> when pfen = 1 and pfcm = 0 the higher 8 bits of adcr and pft values are co mpared when a/d conversion ends and intad is only generated when the higher 8 bits of adcr pft. <2> when pfen = 1 and pfcm = 1 the higher 8 bits of adcr and pft values are co mpared when a/d conversion ends and intad is only generated when the higher 8 bits of adcr < pft. figure 12-11. power-fail detection (when pfen = 1 and pfcm = 0) a/d conversion higher 8 bits of adcr pft intad (pfen = 1) anin anin 80h 80h condition match first conversion note 7fh 80h anin anin note if the conversion result is not read before the end of the next conversion after intad is output, the result is replaced by the next conversion result. remark n = 0 to 7 chapter 12 a/d converter user?s manual u16228ej2v0ud 264 the setting methods are described below. ? when used as a/d conversion operation <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> select the channel and conversion time using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <3> set bit 7 (adcs) of adm to 1. <4> an interrupt request signal (intad) is generated. <5> transfer the a/d conversion data to t he a/d conversion result register (adcr). chapter 12 a/d converter user?s manual u16228ej2v0ud 265 12.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 12-12. overall error figur e 12-13. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 12 a/d converter user?s manual u16228ej2v0ud 266 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 12-14. zero-scale error figure 12-15. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 12-16. integral linearity error figure 12-17. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 12 a/d converter user?s manual u16228ej2v0ud 267 12.6 cautions for a/d converter (1) operating current in standby mode the a/d converter stops operating in the standby mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) of the a/d converter mode register (adm) to 0. figure 12-18 shows the circuit configurati on of the series resistor string. figure 12-18. circuit configuration of series resistor string av ref av ss p-ch series resistor string adcs (2) input range of ani0 to ani7 observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon the end of conversion adcr read has priority. after the read operation, the new conversion result is written to adcr. <2> conflict between adcr write and a/d converter mo de register (adm) write or analog input channel specification register (ads) wr ite upon the end of conversion adm or ads write has priority. adcr write is not pe rformed, nor is the conversion end interrupt signal (intad) generated. chapter 12 a/d converter user?s manual u16228ej2v0ud 268 (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani7. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 12-19, to reduce noise. figure 12-19. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 <1> the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of an i0 to ani7 selected, do not access port 2 while conversion is in progress; otherwise th e conversion resolution may be degraded. <2> if a digital pulse is applied to the pins adjacent to th e pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. since only the leakage current flows other than during sa mpling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, howeve r, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 12-19 ). (7) av ref pin input impedance a series resistor string of several tens of 10 k ? is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. chapter 12 a/d converter user?s manual u16228ej2v0ud 269 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 12-20. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 14 s after the adce bit was set to 1, or if the adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. (10) a/d conversion result register (adcr) read operation when a write operation is performed to the a/d conver ter mode register (adm) and analog input channel specification register (ads), the c ontents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using a timing other than the above may cause an incorrect conversion result to be read. chapter 12 a/d converter user?s manual u16228ej2v0ud 270 (11) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the a/d converter mode register (adm). the delay time exists until actual sampling is st arted after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 12-21 and table 12-3. figure 12-21. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time a/d conversion start delay time sampling time sampling timing intad adcs 1 or ads rewrite sampling time table 12-3. a/d converter sampling time and a/ d conversion start delay time (adm set value) a/d conversion start delay time note fr2 fr1 fr0 conversion time sampling time min. max. 0 0 0 288/f x 40/f x 32/f x 36/f x 0 0 1 240/f x 32/f x 28/f x 32/f x 0 1 0 192/f x 24/f x 24/f x 28/f x 1 0 0 144/f x 20/f x 16/f x 18/f x 1 0 1 120/f x 16/f x 14/f x 16/f x 1 1 0 96/f x 12/f x 12/f x 14/f x other than above setting prohibited ? ? ? note the a/d conversion start delay time is the time after wait period. for the wait function, see chapter 34 cautions for wait . remark f x : x1 clock oscillation frequency (12) register generating wait cycle do not read data from the adcr register and do not wr ite data to the adm, ads, pfm, and pft registers while the cpu is operating on the subsystem clock and while oscillation of the clock input to x1 is stopped. chapter 12 a/d converter user?s manual u16228ej2v0ud 271 (13) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 12-22. internal equi valent circuit of anin pin anin c1 c2 c3 r1 r2 table 12-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf remarks 1. the resistance and capacitance values shown in table 12-4 are not guaranteed values. 2. n = 0 to 7 user?s manual u16228ej2v0ud 272 chapter 13 serial interface uart0 13.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 13.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 13.4.2 asynchronous seri al interface (uart) mode and 13.4.3 dedicated baud rate generator . ? two-pin configuration t x d0: transmit data output pin r x b0: receive data input pin ? length of communication data can be selected from 7 or 8 bits. ? dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? four operating clock inputs selectable ? fixed to lsb-first communication cautions 1. if clock supply to serial interface uart0 is not stoppe d (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops ope rating, and holds the value i mmediately before clock supply was stopped. the t x d0 pin also holds the value imme diately before clock supply was stopped and outputs it. how ever, the operation is not guara nteed after clock supply is resumed. therefore, reset the circuit so th at power0 = 0, rxe0 = 0, and txe0 = 0. 2. set power0 = 1 and then set txe0 = 1 (tr ansmission) or rxe0 = 1 (reception) to start communication. 3. txe0 and rxe0 are sync hronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least tw o clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission ci rcuit or reception circui t may not be initialized. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 273 13.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 13-1. configurati on of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface o peration mode register 0 (asim0) asynchronous serial interface recepti on error status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 1 (pm1) port register 1 (p1) chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 274 figure 13-1. block diagra m of serial interface uart0 t x d0/ sck10/p10 intst0 r x d0/ si10/p11 intsr0 f x /2 5 f x /2 3 f x /2 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) 8-bit timer/ event counter 50 output registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit output latch (p10) pm10 7 7 chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 275 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data conv erted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is tran sferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the rece ive data is not transferred to rxb0. rxb0 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset input or power0 = 0 se ts this register to ffh. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. txs0 can be written by an 8-bit memory manipulatio n instruction. this register cannot be read. reset input, power0 = 0, or txe0 = 0 sets this register to ffh. caution do not write the next tran smit data to txs0 before the tr ansmission completion interrupt signal (intst0) is generated. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 276 13.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following five registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 0 (asim0) this 8-bit register controls the serial comm unication operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. figure 13-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception. notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status r egister 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 277 figure 13-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface reception error status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. to stop the op eration, clear txe0 to 0, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. to stop the operation, clear rxe0 to 0, and then clear power0 to 0. 3. set power0 to 1 and then set rxe0 to 1 wh ile a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 wh ile a low level is input, reception is started. 4. txe0 and rxe0 are sync hronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or recepti on circuit may not be initialized. 5. clear the txe0 and rxe0 bits to 0 be fore rewriting the ps01, ps00, and cl0 bits. 6. make sure that txe0 = 0 when rewriting th e sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. 7. be sure to set bit 0 to 1. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 278 (2) asynchronous serial interface recepti on error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this re gister to 00h if bit 7 (power0) and bit 5 (rxe 0) of asim0 = 0. 00 h is read when this register is read. figure 13-3. format of asynchronous serial inte rface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operati on mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, re gardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 34 cautions for wait. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 279 (3) baud rate generator c ontrol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. figure 13-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk0 ) selection 0 0 tm50 output note 0 1 f x /2 (5 mhz) 1 0 f x /2 3 (1.25 mhz) 1 1 f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 setting prohibited 0 1 0 0 0 8 f xclk0 /8 0 1 0 0 1 9 f xclk0 /9 0 1 0 1 0 10 f xclk0 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 1 0 26 f xclk0 /26 1 1 0 1 1 27 f xclk0 /27 1 1 1 0 0 28 f xclk0 /28 1 1 1 1 0 30 f xclk0 /30 1 1 1 1 1 31 f xclk0 /31 note to select the tm50 output as the bas e clock, start an operation by setting 8-bit timer/event counter 50 so that the duty is 50% of t he output in the pwm mode (bit 6 (tmc506) of the tmc50 register = 1), and then clear tps01 and tps00 to 0. it is not necessary to enable the to50 pin as a timer output pin (bit 0 (toe50) of the tmc register may be 0 or 1). cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring- osc clock, the operation of serial interface uart0 is not guaranteed. 2. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 3. the baud rate value is the output clock of the 5-bit c ounter divided by 2. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 280 remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4. : don?t care 5. figures in parentheses apply to operation at f x = 10 mhz (4) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p10/txd0/sck10 pin for serial interface dat a output, clear pm10 to 0 and set the output latch of p10 to 1. when using the p11/rxd0/si10 pin for serial interface data in put, set pm11 to 1. the output latch of p11 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 13-5. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 281 13.4 operation of serial interface uart0 serial interface uart0 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 13.4.1 operation stop mode in this mode, serial communication cannot be executed, thus reducing the power consumption. in addition, the pins can be used as ordinary port pins in this mode. to se t the operation stop mode, clear bits 7, 6, and 5 (power0, txe0, and rxe0) of asim0 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status r egister 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. caution clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the operation, set power0 to 1, and then set txe0 and rxe0 to 1. remark to use the rxd0/si10/p11 and txd0/sck10/p10 pins as general-purpose port pins, see chapter 4 port functions . chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 282 13.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the brgc0 register (see figure 13-4 ). <2> set bits 1 to 4 (sl0, cl0, ps00, and ps01) of the asim0 register (see figure 13-2 ). <3> set bit 7 (power0) of the asim0 register to 1. <4> set bit 6 (txe0) of the asim0 register to 1. transmission is enabled. set bit 5 (rxe0) of the asim0 register to 1. reception is enabled. <5> write data to the txs0 register. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 13-2. relationship between register settings and pins pin function power0 txe0 rxe0 pm10 p10 pm11 p11 uart0 operation txd0/sck10/p10 rxd0/si10/p11 0 0 0 note note note note stop sck10/p10 si10/p11 0 1 note note 1 reception sck10/p10 rxd0 1 0 0 1 note note transmission txd0 si10/p11 1 1 1 0 1 1 transmission/ reception txd0 rxd0 note can be set as port function. remark : don?t care power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 pm1: port mode register p1: port output latch chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 283 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 13-6 and 13-7 show the format and waveform example of the normal transmit/receive data. figure 13-6. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (asim0). figure 13-7. example of normal uart transmit/receive data waveform 1. data length: 8 bits, parity: even pari ty, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity , stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, pa rity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 284 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no par ity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 285 (c) transmission the t x d0 pin outputs a high level when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1. if bit 6 (txe0) of asim0 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the start bit is output from the t x d0 pin, followed by t he rest of the data in order starting from the lsb. when transmission is co mpleted, the parity and stop bits set by asim0 are appended and a transmission completion inte rrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 13-8 shows the timing of the transmission comp letion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 13-8. transmission comple tion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 286 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator st arts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 13-9). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, recept ion is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the st op bit has been received, the reception completion interrupt (intsr0) is generated and t he data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (int sr0) is generated after completion of reception. figure 13-9. reception completi on interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. be sure to read receive buffer register 0 (rxb0) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 0 (asis0) before reading rxb0. chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 287 (e) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 0 (asis0) is set as a result of data reception, a reception error interrupt request (intsr0) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis0 in the reception error interrupt servicing (intsr0) (see figure 13-3 ). the contents of asis0 are reset to 0 when asis0 is read. table 13-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 13- 10, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 13-10. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 288 13.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a sour ce clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator control register 0 (brgc0) is supplied to each module when bit 7 (power0) of asyn chronous serial interface operation mode register 0 (asim0) is 1. this clock is called the base clock and its frequency is called f xclk0 . the base clock is fixed to low level when power0 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 13-11. configuration of baud rate generator f xclk0 selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 8-bit timer/ event counter 50 output f x /2 5 f x /2 f x /2 3 baud rate generator remark power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0 chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 289 (2) generation of serial clock a serial clock can be generated by using baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value of the 5-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk0 : frequency of base clock selected by the tps 01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of t he brgc0 register (k = 8, 9, 10, ..., 31) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] f xclk0 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 290 (3) example of setting baud rate table 13-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] 2400 ? ? ? ? ? ? ? ? 3 27 2425 1.03 4800 ? ? ? ? 3 27 4850 1.03 3 14 4676 ? 2.58 9600 3 16 9766 1.73 3 14 9353 ? 2.58 2 27 9699 1.03 10400 3 15 10417 0.16 3 13 10072 ? 3.15 2 25 10475 0.72 19200 3 8 19531 1.73 2 27 19398 1.03 2 14 18705 ? 2.58 31250 2 20 31250 0 2 17 30809 ? 1.41 ? ? ? ? 38400 2 16 39063 1.73 2 14 38796 ? 2.58 2 27 38796 1.03 76800 2 8 78125 1.73 1 27 77593 1.03 1 14 74821 ? 2.58 115200 1 22 113636 ? 1.36 1 18 116389 1.03 1 9 116389 1.03 153600 1 16 156250 1.73 1 14 149643 ? 2.58 ? ? ? ? 230400 1 11 227273 ? 1.36 1 9 232778 1.03 ? ? ? ? remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk0 )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f x : x1 input clock oscillation frequency err: baud rate error chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 291 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 13-12. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 13-12, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 0 (brgc0) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks chapter 13 serial interface uart0 user?s manual u16228ej2v0ud 292 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 13-5. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 user?s manual u16228ej2v0ud 293 chapter 14 serial interface uart6 14.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 14.4.2 asynchronous seri al interface (uart) mode and 14.4.3 dedicated baud rate generator . ? two-pin configuration t x d6: transmit data output pin r x b6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? twelve operating clock inputs selectable ? msb- or lsb-first communication selectable ? inverted transmission operation ? synchronous break field transmission from 13 to 20 bits ? more than 11 bits can be identified for synchronous break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side and not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops ope rating, and holds the value i mmediately before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. how ever, the operation is not guara nteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. if data is continuously transmitted, the communication timi ng from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the recepti on side initializes the timing when it has detected a start bit. do not use the contin uous transmission function if the interface is incorporated in lin. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 294 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 295 figure 14-2. lin reception operation sleep bus 13 bits note 2 sf reception id reception data reception data reception data reception note 5 note 3 note 1 note 4 wakeup signal frame synchronous break field synchronous field indent field data field data field checksum field rx6 sbf reception reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when an sbf wit h low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if an sbf with low-level da ta of less than 11 bits has been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of ua rt communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the bit length of the synchronous field, disable uart6 after sf reception, and then re-set baud rate gen erator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processi ng by software to initialize uart6 after reception of the checksum field an d to set the sbf reception mode again. to perform a lin receive operation, use a conf iguration like the one shown in figure 14-3. the wakeup signal transmitted from the lin master is re ceived by detecting the edge of the external interrupt (intp0). the length of the synchronous field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, and the bau d rate error can be calculated. the input signal of the reception port input (rxd6) ca n be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without co nnecting rxd6 and intp0/ti000 externally. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 296 figure 14-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p14/rxd6 p120/intp0 p00/ti000 port input switch control (isc0) chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 297 14.2 configuration of serial interface uart6 serial interface uart6 includes the following hardware. table 14-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1) chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 298 figure 14-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ p13 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p14 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p13) pm13 8 selector note selectable with input switch control register (isc). chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 299 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from rxs6. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset input sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset input sets this register to ffh. cautions 1. do not write data to txb6 when bi t 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchr onous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 300 14.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 14-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enables operation of the internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. 3. operation of the 8-bit counter out put is enabled at the second base clock after 1 is written to the power6 bit. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 301 figure 14-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. to stop the op eration, clear txe6 to 0, and then clear power6 to 0. 2. at startup, set power6 to 1 and then set rxe6 to 1. to stop the operation, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 wh ile a high level is input to the rxd6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 5. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 6. make sure that txe6 = 0 wh en rewriting the sl6 bit. recep tion is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 7. make sure that rxe6 = 0 when rewriting the isrm6 bit. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 302 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this re gister to 00h if bit 7 (power6) and bit 5 (rxe 6) of asim6 = 0. 00 h is read when this register is read. figure 14-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 34 cautions for wait. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 303 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset input clears this register to 00h if bi t 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 14-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 304 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is writ ten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 14-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection 0 0 0 0 f x (10 mhz) 0 0 0 1 f x /2 (5 mhz) 0 0 1 0 f x /2 2 (2.5 mhz) 0 0 1 1 f x /2 3 (1.25 mhz) 0 1 0 0 f x /2 4 (625 khz) 0 1 0 1 f x /2 5 (312.5 khz) 0 1 1 0 f x /2 6 (156.25 khz) 0 1 1 1 f x /2 7 (78.13 khz) 1 0 0 0 f x /2 8 (39.06 khz) 1 0 0 1 f x /2 9 (19.53 khz) 1 0 1 0 f x /2 10 (9.77 khz) 1 0 1 1 tm50 output note other than above setting prohibited note to select the output of tm50 as t he base clock, start the operation by setting 8-bit timer/event counter 50 so that the duty is 50% of t he output in the pwm mode (bit 6 (tmc506) of the tmc50 register = 1), and then set tps63, tps62, tps61, and tps60 to 1, 0, 1, and 1, respectively. it is not necessary to enable the to50 pin as a timer output pin (bit 0 (toe 50) of the tmc register may be 0 or 1). cautions 1. when the ring -osc clock is selected as th e clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring- osc clock, the operation of serial interface uart6 is not guaranteed. 2. make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 305 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 14-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 setting prohibited 0 0 0 0 1 0 0 0 8 f xclk6 /8 0 0 0 0 1 0 0 1 9 f xclk6 /9 0 0 0 0 1 0 1 0 10 f xclk6 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (r xe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don?t care chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 306 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). note, however, that comm unication is started by the refresh operation because bit 6 (sbrt6) of asicl6 is cleared to 0 when communication is completed (when an interrupt signal is generated). figure 14-10. format of asynchronous serial interface control register 6 (asicl6) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 0 1 0 1 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger dir6 first bit specification 0 msb 1 lsb txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 note bits 2 to 5 and 7 are read-only. cautions 1. in the case of an sbf reception error, return the mode to the sb f reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bi t, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been co rrectly completed. 4. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 307 (7) input switch control register (isc) the input switch control register (isc) is used to receiv e a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 14-11. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p00) 1 rxd6 (p14) isc0 intp0 input source selection 0 intp0 (p120) 1 rxd6 (p14) (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/txd3 pin for serial interface data out put, clear pm13 to 0 and set the output latch of p13 to 1. when using the p14/rxd6 pin for serial interface data input, set pm14 to 1. the output latch of p14 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 14-12. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 308 14.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 14.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary port pins in this mode. to set the operation st op mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6 enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing txe6 and rxe6 to 0 to set the operation stop mode. to start the operation, set power6 to 1, and then set txe6 and rxe6 to 1. remark to use the rxd6/p14 and txd6/p13 pins as general-purpose port pins, see chapter 4 port functions . chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 309 14.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 14-8 ). <2> set the brgc6 register (see figure 14-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 14-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 14-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 310 the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm13 p13 pm14 p14 uart6 operation txd6/p13 rxd6/p14 0 0 0 note note note note stop p13 p14 0 1 note note 1 reception p13 rxd6 1 0 0 1 note note transmission txd6 p14 1 1 1 0 1 1 transmission/ reception txd6 rxd6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm1: port mode register p1: port output latch chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 311 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-13 and 14-14 show the format and waveform example of the normal transmit/receive data. figure 14-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 312 figure 14-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 313 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 wh en the device is inco rporated in lin. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no par ity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 314 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the data is sequentially out put from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 14-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 14-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 315 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference the asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asis register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is incorp orated in a lin, the continuous transmission function cannot be used. make sure that a synchronous serial interface tran smission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmission unit upon completion of continuous transmission, be sure to check that the txsf6 flag is ?0? afte r generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmission, an ove rrun error may occur, which means that the next transmission was completed before exe cution of intst6 interrupt servicing after transmission of one data frame. an ove rrun error can be detected by developing a program that can count the number of transmit data and by refere ncing the txsf6 flag. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 316 figure 14-16 shows an example of the continuous transmission processing flow. figure 14-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 317 figure 14-17 shows the timing of starting continuous transmission, and figure 14-18 shows the timing of ending continuous transmission. figure 14-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 318 figure 14-18. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 319 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 14-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6 /intsre6) is generated on completion of reception. figure 14-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. be sure to read receive buffer register 6 (rxb6) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 320 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (see figure 14-6 ). the contents of asis6 are reset to 0 when asis6 is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous se rial interface operation mode register 6 (asim6) to 0. figure 14-20. reception error interrupt 1. if isrm6 is cleared to 0 (reception completion in terrupt (intsr6) and erro r interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 321 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in lin, the sbf (syn chronous break field) transmission control function is used for transmission. for the tr ansmission operation of lin, see figure 14-1 lin transmission operation . sbf transmission is used to transmit an sbf length that is a low-level widt h of 13 bits or more by adjusting the baud rate value of the ordi nary uart transmission function. [setting method] transmit 00h by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. this enables a low-level transmi ssion of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). adjust the baud rate value to adjust this 10 -bit low level to the targeted sbf length. example if lin is to be transmitted under the following conditions ? base clock of uart6 = 5 mhz (set by clock selection register 6 (cksr6)) ? target baud rate value = 19200 bps to realize the above baud rate value, the length of a 13-bit sbf is as follows if the baud rate generator control register 6 (brgc6) is set to 130. ? 13-bit sbf length = 0.2 s 130 2 13 = 676 s to realize a 13-bit sbf length in 10 bits, set a value 1.3 times the targeted baud rate to brgc6. in this example, set 169 to brgc6. the transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit sbf length. ? 10-bit low-level transmission length = 0.2 s 169 2 10 = 676 s chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 322 if the number of bits set by brgc6 runs short, adjus t the number of bits by setting the base clock of uart6. figure 14-22. example of setting proced ure of sbf transmission (flowchart) start read brgc6 register and save current set value of brgc6 register to general- purpose register. clear txe6 and rxe6 bits of asim6 register to 0 (to disable transmission/ reception). set value to brgc6 register to realize desired sbf length. set character length of data to 8 bits and parity to 0 or even using asim6 register. set txe6 bit of asim6 register to 1 to enable transmission. set txb6 register to "00h" and start transmission. intst6 occurred? no yes clear txe6 and rxe6 bits of asim6 register to 0. rewrite saved brgc6 value to brgc6 register. re-set ps61 bit, ps60 bit, and cl6 bit of asim6 register to desired value. set txe6 bit of asim6 register to 1 to enable transmission. end figure 14-23. sbf transmission t x d6 intst6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 323 (i) sbf reception when the device is incorporated in lin, the sbf (syn chronous break field) reception control function is used for reception. for the re ception operation of lin, see figure 14-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is st arted, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. wh en the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the wi dth of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 14-24. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 324 14.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selection register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 325 figure 14-25. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 326 (2) generation of serial clock a serial clock can be generated by using clock selecti on register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of br gc6 register (k = 8, 9, 10, ..., 255) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m/(2 33) = 10000000/(2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) f xclk6 2 k chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 327 (3) example of setting baud rate table 14-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 101 10371 0.28 1h 101 10475 ? 0.28 19200 1h 130 19231 0.16 1h 109 19200 0.11 0h 109 19220 0.11 31250 1h 80 31250 0.00 0h 134 31268 0.06 0h 67 31268 0.06 38400 0h 130 38462 0.16 0h 109 38440 0.11 0h 55 38090 ? 0.80 76800 0h 65 76923 0.16 0h 55 76182 ? 0.80 0h 27 77593 1.03 115200 0h 43 116279 0.94 0h 36 116388 1.03 0h 18 116389 1.03 153600 0h 33 151515 ? 1.36 0h 27 155185 1.03 0h 14 149643 ? 2.58 230400 0h 22 227272 ? 1.36 0h 18 232777 1.03 0h 9 232778 1.03 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f x : x1 input clock oscillation frequency err: baud rate error chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 328 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-26. permissible baud rate range during reception fl 1 data frame (11 ? chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 329 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-5. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k chapter 14 serial interface uart6 user?s manual u16228ej2v0ud 330 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 14-27. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 user?s manual u16228ej2v0ud 331 chapter 15 serial interfaces csi10 and csi11 the pd780131 and 780132 incorporate serial interface csi10, and the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 incorporate seri al interfaces csi10 and csi11. 15.1 functions of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 have the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is used to communicate 8-bit data using three lines: a serial clock line (sck1n) and two serial data lines (si1n and so1n). the processing time of data communication can be shortened in the 3-wire seri al i/o mode bec ause transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated with the m sb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is used for connecting periphe ral ics and display controllers with a clocked serial interface. for details, see 15.4.2 3-wire serial i/o mode . chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 332 15.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 include the following hardware. table 15-1. configuration of serial interfaces csi10 and csi11 item configuration registers transmit buffer register 1n (sotb1n) serial i/o shift re gister 1n (sio1n) transmit controller clock start/stop controller & clock phase controller control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) port mode register 0 (pm0) or port mode register 1 (pm1) port register 0 (p0) or port register 1 (p1) remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 15-1. block diagram of serial interface csi10 internal bus si10/p11/r x d0 intcsi10 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 sck10/p10/txd0 transmit buffer register 10 (sotb10) transmit controller clock start/stop controller & clock phase controller serial i/o shift register 10 (sio10) output selector so10/p12 output latch 8 transmit data controller 8 output latch (p12) pm12 selector chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 333 figure 15-2. block diagram of serial interface csi11 ( chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 334 15.3 registers controlling seri al interfaces csi10 and csi11 serial interfaces csi10 and csi11 are cont rolled by the following four registers. ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 0 (pm0) or port mode register 1 (pm1) ? port register 0 (p0) or port register 1 (p1) (1) serial operation mode register 1n (csim1n) csim1n is used to select the operation m ode and enable or disable operation. csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 15-3. format of serial oper ation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd10 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 6 first bit specification 0 msb 1 lsb csot10 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. when using as a general-purpose port, see caution 3 of figure 15-5 and table 15-2 . 3. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 4. do not rewrite trmd10 when csot10 = 1 (during serial communication). 5. the so10 output is fixed to the low level when trmd 10 is 0. reception is started when data is read from sio10. 6. do not rewrite dir10 when csot10 = 1 (during serial communication). caution be sure to clear bit 5 to 0. chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 335 figure 15-4. format of serial oper ation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd11 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 6, 7 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 8 first bit specification 0 msb 1 lsb csot11 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. when using as a general-purpose port, see caution 3 of figure 15-6 and table 15-2 . 3. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 4. do not rewrite trmd11 when csot11 = 1 (during serial communication). 5. the so11 output is fixed to the low level when trmd 11 is 0. reception is started when data is read from sio11. 6. do not rewrite sse11 when csot11 = 1 (during serial communication). 7. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 8. do not rewrite dir11 when csot11 = 1 (during serial communication). chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 336 (2) serial clock selecti on register 1n (csic1n) this register specifies the timing of the data transmission/reception and sets the serial clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 figure 15-5. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 se rial clock selection mode 0 0 0 f x /2 (5 mhz) master mode 0 0 1 f x /2 2 (2.5 mhz) master mode 0 1 0 f x /2 3 (1.25 mhz) master mode 0 1 1 f x /2 4 (625 khz) master mode 1 0 0 f x /2 5 (312.5 khz) master mode 1 0 1 f x /2 6 (156.25 khz) master mode 1 1 0 f x /2 7 (78.13 khz) master mode 1 1 1 external clock input to sck10 slave mode chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 337 cautions 1. when the ring-osc clo ck is selected as the clock supplied to the cpu, the clock of the ring- osc oscillator is divided and supp lied as the serial clock. at th is time, the operation of serial interface csi10 is not guaranteed. 2. do not write to csic10 while csie10 = 1 (operation enabled). 3. clear ckp10 to 0 to use p10/sck10/txd0, p11/si10/rxd0, and p12/so10 as general-purpose port pins. 4. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 338 figure 15-6. format of serial clo ck selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 cks112 cks111 cks110 csi11 se rial clock selection mode 0 0 0 f x /2 (5 mhz) master mode 0 0 1 f x /2 2 (2.5 mhz) master mode 0 1 0 f x /2 3 (1.25 mhz) master mode 0 1 1 f x /2 4 (625 khz) master mode 1 0 0 f x /2 5 (312.5 khz) master mode 1 0 1 f x /2 6 (156.25 khz) master mode 1 1 0 f x /2 7 (78.13 khz) master mode 1 1 1 external clock input to sck11 slave mode cautions 1. when the ring-osc clo ck is selected as the clock supplied to the cpu, the clock of the ring- osc oscillator is divided and supp lied as the serial clock. at th is time, the operation of serial interface csi11 is not guaranteed. 2. do not write to csic11 while csie11 = 1 (operation enabled). 3. clear ckp11 to 0 to use p0 2/so11, p03/si11, and p04/sck11 as general-purpose port pins. 4. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 339 (3) port mode registers 0 and 1 (pm0, pm1) these registers set port 0 and 1 input/output in 1-bit units. when using p10/sck10 and p04/sck11 note as the clock output pins of t he serial interface, and p12/so10 and p02/so11 note as the data output pins, clear pm10, pm04, pm12, pm02, and the output latches of p10, p04, p12, and p02 to 0. when using p10/sck10 and p04/sck11 note as the clock input pins of the serial interface, p11/si10/rxd0 and p03/si11 note as the data input pins, and p05/ ssi11/ti001 as the chip select i nput pin, set pm10, pm04, pm11, pm03, and pm05 to 1. at this time, the output latches of p10, p04, p11, p03, and p05 may be 0 or 1. pm0 and pm1 can be set by a 1-bit or 8- bit memory manipulation instruction. reset input sets these registers to ffh. note pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. figure 15-7. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) figure 15-8. format of port mode register 1 (pm1) 7 pm17 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 symbol pm1 address: ff21h after reset: ffh r/w pm1n 0 1 p1n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 340 15.4 operation of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 15.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10/t x d0, p11/si10/r x d0, p12/so10, p02/so11 note , p03/si11 note , and p04/sck11 note pins can be used as ordinary i/o port pins in this mode. note pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only (1) register used the operation stop mode is set by serial operation mode register 1n (csim1n). to set the operation stop mode, clear bit 7 (csie1n) of csim1n to 0. (a) serial operation mode register 1n (csim1n) csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1n to 00h. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use the si10/rxd0/p11, so 10/p12, and sck10/txd0/p10 pins as general-purpose port pins, see chapter 4 port functions . 2. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use the si11/p03, so11/ p02, sck11/p04, and ssi11/ti 001/p05 pins as general-purpose port pins, see chapter 4 port functions . 2. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 341 15.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controll ers with a clocked serial interface. in this mode, communication is executed by using three li nes: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) registers used ? ? ? ? chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 342 the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins (1/2) (a) serial interface csi10 pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation si10/rxd0/ p11 so10/p12 sck10/ txd0/p10 0 note 1 note 1 note 1 note 1 note 1 note 1 stop rxd0/p11 p12 txd0/ p10 note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 p12 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 rxd0/p11 so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 p12 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission rxd0/p11 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p10/sck10/txd0 as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1: port mode register p1: port output latch chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 343 table 15-2. relationship between register settings and pins (2/2) (b) serial interface csi11 ( chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 344 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is writt en to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of seri al operation mode register 1n (csim1n) is 0. reception is started when dat a is read from serial i/o shift register 1n (sio1n). however, communication is performed as follows if bit 5 (s se11) of csim11 is 1 when serial interface csi11 is in the slave mode. <1> low level input to the ssi11 pin transmission/reception is started when sotb11 is writt en, or reception is star ted when sio11 is read. <2> high level input to the ssi11 pin transmission/reception or reception is held, therefore, even if sotb11 is written or sio11 is read, transmission/reception or rece ption will not be started. <3> data is written to sotb11 or data is read from sio 11 while a high level is input to the ssi11 pin, then a low level is input to the ssi11 pin transmission/reception or reception is started. <4> a high level is input to the ssi11 pi n during transmission/reception or reception transmission/reception or reception is suspended. after communication has been started, bi t 0 (csot1n) of csim1n is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1n) is set, and csot1n is cleared to 0. then the next communication is enabled. cautions 1. do not access the control register an d data register when csot1n = 1 (during serial communication). 2. when using serial interface csi11, wait fo r the duration of at least one clock before the clock operation is started to ch ange the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 345 figure 15-9. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception timing (t ype 1; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 346 figure 15-9. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception timing (t ype 2; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 347 figure 15-10. timing of clock/data phase (a) type 1; ckp1n = 0, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2; ckp1n = 0, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3; ckp1n = 1, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4; ckp1n = 1, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 348 (3) timing of output to so1n pin (first bit) when communication is started, the value of transmit buffe r register 1n (sotb1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 15-11. output operation of first bit (1) when ckp1n = 0, dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch the first bit is directly latched by the sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output selector. th en, the value of the sotb1n register is transferred to the sio1n register at the next rising (or fa lling) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. (2) when ckp1n = 0, dap1n = 1 (or ckp1n = 1, dap1n = 1) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch the first bit is directly latched by the sotb1n register at the falling edge of the write signal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transfe rred to the sio1n register at the next falling (or rising) edge of sck1n, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the out put latch at the next rising (or falling) edge of sck1n, and the data is output from the so1n pin. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 349 (4) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 15-12. output value of so1n pin (last bit) (1) type 1; when ckp1n = 0 and dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n ( next request is issued.) last bit output latch (2) type 2; when ckp1n = 0 and dap1n = 1 (or ckp1n = 1, dap1n = 1) sck1n sotb1n sio1n so1n last bit writing to sotb1n or reading from sio1n ( next request is issued.) output latch remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 chapter 15 serial interfaces csi10 and csi11 user?s manual u16228ej2v0ud 350 (5) so1n output the status of the so1n output is as follows if bit 7 (csie1n) of serial operation mode register 1n (csim1n) is cleared to 0. table 15-3. so1n output status trmd1n dap1n dir1n so1n output trmd1n = 0 note ? ? outputs low level note . dap1n = 0 ? value of so1n latch (low-level output) dir1n = 0 value of bit 7 of sotb1n trmd1n = 1 dap1n = 1 dir1n = 1 value of bit 0 of sotb1n note status after reset caution if a value is written to trmd1n, dap1n, and dir1n, the output value of so1n changes. remark n = 0: pd780131, 780132 n = 0, 1: pd780133, 780134, 78f0134, 780136, 780138, 78f0138 user?s manual u16228ej2v0ud 351 chapter 16 multiplier/divider 16.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 16 bits = 32 bits, 16-bit remainder (division) 16.2 configuration of multiplier/divider the multiplier/divider incl udes the following hardware. table 16-1. configuration of multiplier/divider item configuration registers remainder data register 0 (sdr0) multiplication/division data r egisters a0 (mda0h, mda0l) multiplication/division dat a registers b0 (mdb0) control register multiplier/divider control register 0 (dmuc0) figure 16-1 shows the block diagram of the multiplier/divider. chapter 16 multiplier/divider user?s manual u16228ej2v0ud 352 figure 16-1. block diagra m of multiplier/divider internal bus cpu clock start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h + mdb0l) remainder data register 0 (sdr0 (sdr0h + sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 ( mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll) ) controller dmue mda000 intdmu chapter 16 multiplier/divider user?s manual u16228ej2v0ud 353 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. th is register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. this register can be read by an 8-bit or 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 16-2. format of remainder data register 0 (sdr0) address: ff60h, ff61h after reset: 0000h r symbol ff61h (sdr0h) ff60h (sdr0l) sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 duri ng operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1). (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a 32-bit register that sets a 16-bit multiplier a in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the oper ation (higher 16 bits: mda0h, lower 16 bits: mda0l). figure 16-3. format of mult iplication/division data regi ster a0 (mda0h, mda0l) address: ff62h, ff63h, ff64h, ff65h after reset: 0000h, 0000h r/w symbol ff65h (mda0hh) ff64h (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff63h (mda0lh) ff62h (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is cleared to 0 when an operation is starte d in the multiplication mode (when multiplier/divider control regist er 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 duri ng operation processing (whi le bit 7 (dmue) of multiplier/divider control regi ster 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 3. the value read from mda0 during oper ation processing (while dmue is 1) is not guaranteed. chapter 16 multiplier/divider user?s manual u16228ej2v0ud 354 the functions of mda0 when an operation is executed are shown in the table below. table 16-2. functions of mda0 during operation execution dmusel0 operation mode setting operation result 0 division mode di vidend division result (quotient) 1 multiplication mode higher 16 bits: 0, lower 16 bits: multiplier a multiplication result (product) the register configuration differs between when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication chapter 16 multiplier/divider user?s manual u16228ej2v0ud 355 16.3 register controlling multiplier/divider the multiplier/divider is controlled by mult iplier/divider control register 0 (dmuc0). (1) multiplier/divider c ontrol register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. this register can be read by a 1-bit or 8-bit memory manipula tion instruction. reset input clears this register to 00h. figure 16-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff68h after reset: 00h r/w symbol 4 3 2 1 0 6 <7> 5 note when dmue is set to 1, the operati on is started. dmue is automatically cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during ope ration processing (when dmue is 1), the operation result is not guaranteed. if the operation is comple ted while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (while dmue is 1). if it is changed, undefined operation resu lts are stored in multiplicati on/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during opera tion processing (while dmue is 1), the operation processing is stopped. to execute the operati on again, set multiplication/division data register a0 (mda0), multiplication/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and start the operation (by clearing dmue to 1). chapter 16 multiplier/divider user?s manual u16228ej2v0ud 356 16.4 operations of multiplier/divider 16.4.1 multiplication operation ? initial setting 1. set operation data to multiplicati on/division data register a0l (mda0l) a nd multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divi der control register 0 (dmuc0) to 1. operation will start. ? during operation 3. the operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0 h registers during operati on, and therefore the read values of these registers are not guaranteed). ? end of operation 4. the operation result data is stor ed in the mda0l and mda0h registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 16.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 16.4.2 division operation . chapter 16 multiplier/divider user?s manual u16228ej2v0ud 357 figure 16-6. timing chart of multiplication operation (00dah chapter 16 multiplier/divider user?s manual u16228ej2v0ud 358 16.4.2 division operation ? initial setting 1. set operation data to multiplica tion/division data register a0 (mda0l and mda0h) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. operation will start. ? during operation 3. the operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0 h registers and remainder data register 0 (sdr0) during operation, and theref ore the read values of these registers are not guaranteed). ? end of operation 4. the result data is stored in th e mda0l, mda0h, and sdr0 registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 16.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 16.4.2 division operation . chapter 16 multiplier/divider user?s manual u16228ej2v0ud 359 figure 16-7. timing chart of division operation (dcba2586h user?s manual u16228ej2v0ud 360 chapter 17 interrupt functions 17.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see table 17-1 ). a standby release signal is generated a nd stop and halt modes are released. nine external interrupt requests and 19 (16 in the pd780131 and 780132) internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 17.2 interrupt sources and configuration a total of 29 (26 in the pd780131 and 780132) interrupt sources exist for maskable and software interrupts (see table 17-1 ). chapter 17 interrupt functions user?s manual u16228ej2v0ud 361 table 17-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and crh1 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and crh0 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad end of a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intwti watch timer referenc e time interval signal 0028h 19 inttm51 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) 20 intkr key interrupt detection external 002ch (c) 21 intwt watch timer overflow internal 002eh (a) 22 intp6 0030h maskable 23 intp7 pin input edge detection external 0032h (b) notes 1. the default priority is the prio rity applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 27 is the lowest. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 17-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 0. chapter 17 interrupt functions user?s manual u16228ej2v0ud 362 table 17-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 24 intdmu end of multiply/divide operation 0034h 25 intcsi11 note 3 end of csi11 communication 0036h 26 inttm001 note 3 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 0038h maskable 27 inttm011 note 3 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) internal 003ah (a) software ? brk brk instruction execution ? 003eh (d) reset reset input poc power-on clear note 4 lvi low-voltage detection note 5 clock monitor x1 oscillation stop detection reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the prio rity applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 27 is the lowest. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 17-1. 3. the interrupt sources intcsi11, inttm001, and inttm011 are available only in the pd780133, 780134, 78f0134, 780136, 780138, and 78f0138. 4. when ?poc used? is selected by a mask option. 5. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. chapter 17 interrupt functions user?s manual u16228ej2v0ud 363 figure 17-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp7) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag chapter 17 interrupt functions user?s manual u16228ej2v0ud 364 figure 17-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 7) (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register 17.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regist er (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 17-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. chapter 17 interrupt functions user?s manual u16228ej2v0ud 365 table 17-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt request register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 dualif0 note 1 dualmk0 note 2 dualpr0 note 2 intst0 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif if1l admk mk1l adpr pr1l intsr0 srif0 srmk0 srpr0 intwti wtiif wtimk wtipr inttm51 tmif51 tmmk51 tmpr51 intkr krif krmk krpr intwt wtif wtmk wtpr intp6 pif6 pmk6 ppr6 intp7 pif7 pmk7 ppr7 intdmu dmuif if1h dmumk mk1h dmupr pr1h intcsi11 note 3 csiif11 note 3 csimk11 note 3 csipr11 note 3 inttm001 note 3 tmif001 note 3 tmmk001 note 3 tmpr001 note 3 inttm011 note 3 tmif011 note 3 tmmk011 note 3 tmpr011 note 3 notes 1. if either of the two types of interrupt s ources is generated, these flags are set (1). 2. both types of interrupt sources are supported. 3. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. chapter 17 interrupt functions user?s manual u16228ej2v0ud 366 (1) interrupt request flag regist ers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruct ion. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are read with a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 17-2. format of interrupt request fl ag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 <3> <2> <1> <0> if1h 0 note 1 0 note 1 0 note 1 0 note 1 tmif011 note 2 tmif001 note 2 csiif11 note 2 dmuif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. be sure to set bits 4 to 7 of if1h to 0. 2. pd780133, 780134, 78f0134, 780136, 780138, an d 78f0138 only. be sure to set the pd780131 and 780132 to 0. cautions 1. when operating a timer, serial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 2. if an interrupt request corresponding to a fl ag of the interrupt requ est flag register is generated while the interrupt re quest flag register is being manipulated (including by 1-bit memory manipulation), the flag corresponding to the interrupt request may not be set to 1. chapter 17 interrupt functions user?s manual u16228ej2v0ud 367 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8- bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set with a 16-bit memory manipulation instruction. reset input sets mk0l, mk0h, and mk1l to ffh and sets mk1h to dfh. figure 17-3. format of interrupt mask fl ag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: dfh r/w symbol 7 6 5 4 <3> <2> <1> <0> mk1h 1 note 1 1 note 1 0 note 1 1 note 1 tmmk011 note 2 tmmk001 note 2 csimk11 note 2 dmumk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. be sure to set bits 4, 6, and 7 of mk1h to 1. be sure to clear bit 5 of mk1h to 0. 2. pd780133, 780134, 78f0134, 780136, 780138, an d 78f0138 only. be sure to set the pd780131 and 780132 to 1. chapter 17 interrupt functions user?s manual u16228ej2v0ud 368 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bi t memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 17-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpro stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 <3> <2> <1> <0> pr1h 1 note 1 1 note 1 1 note 1 1 note 1 tmpr011 note 2 tmpr001 note 2 csipr11 note 2 dmupr xxprx priority level selection 0 high priority level 1 low priority level notes 1. be sure to set bits 4 to 7 of pr1h to 1. 2. pd780133, 780134, 78f0134, 780136, 780138, an d 78f0138 only. be sure to set the pd780131 and 780132 to 1. chapter 17 interrupt functions user?s manual u16228ej2v0ud 369 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 17-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp egp7 epg6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 17-3 shows the ports corresponding to egpn and egnn. table 17-3. ports correspo nding to egpn and egnn detection enable register edge dete ction port external request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 7 chapter 17 interrupt functions user?s manual u16228ej2v0ud 370 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 17-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 17 interrupt functions user?s manual u16228ej2v0ud 371 17.4 interrupt servicing operations 17.4.1 maskable interrupt acknowledgement a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt r equest (when the isp flag is re set to 0). the times from generation of a maskable interrupt reques t until interrupt servicing is perfor med are listed in table 17-4 below. for the interrupt request acknowledgement timing, see figures 17-8 and 17-9 . table 17-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 17-7 shows the interrupt request acknowledgement algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data deter mined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 17 interrupt functions user?s manual u16228ej2v0ud 372 figure 17-7. interrupt request ac knowledgement pr ocessing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interr upt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledg ed, or low-priority interrupt servicing) chapter 17 interrupt functions user?s manual u16228ej2v0ud 373 figure 17-8. interrupt request ac knowledgement timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 17-9. interrupt request ac knowledgement timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 17.4.2 software interrupt request acknowledgement a software interrupt acknowledge is acknowledged by br k instruction execution. software interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. chapter 17 interrupt functions user?s manual u16228ej2v0ud 374 17.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the in terrupt request acknowledgem ent enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgement becomes disabled (ie = 0). therefore, to enable multiple interrupt se rvicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgement. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt current ly being serviced is generated during interr upt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pe nding. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 17-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 17-10 shows multiple interrupt servicing examples. table 17-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { { maskable interrupt isp = 1 { { { software interrupt { { { remarks 1. : multiple interrupt servicing enabled 2. chapter 17 interrupt functions user?s manual u16228ej2v0ud 375 figure 17-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled chapter 17 interrupt functions user?s manual u16228ej2v0ud 376 figure 17-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgement disabled chapter 17 interrupt functions user?s manual u16228ej2v0ud 377 17.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for t hem while another instruction is being executed, request acknowledgement is held pending until t he end of execution of the next instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers. caution the brk instruction is not one of the above-lis ted interrupt request hold instructions. however, the software interrupt activated by executing the brk instructi on causes the ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. figure 17-11 shows the timing at which interrupt requests are held pending. figure 17-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (instruction request). user?s manual u16228ej2v0ud 378 chapter 18 key interrupt function 18.1 functions of key interrupt a key interrupt (intkr) can be generated by setting the key return mode register (krm) and inputting a rising edge to the key interrupt input pins (kr0 to kr7). table 18-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 18.2 configuration of key interrupt the key interrupt includes the following hardware. table 18-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 18-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 edge detector chapter 18 key interrupt function user?s manual u16228ej2v0ud 379 18.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. this register is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 18-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request fl ag may be set. therefo re, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. user?s manual u16228ej2v0ud 380 chapter 19 standby function 19.1 standby function and configuration 19.1.1 standby function table 19-1. relationship between operat ion clocks in each operation status x1 oscillator ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode mstop = 0 mcc = 0 mstop = 1 mcc = 1 note 1 rstop = 0 rstop = 1 subsystem clock oscillator cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating stopped oscillating oscillating stopped oscillating note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution sets the ha lt mode. in the halt mode, the cpu operation clock is stopped. if the x1 oscillator, ring-osc oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. chapter 19 standby function user?s manual u16228ej2v0ud 381 (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the x1 oscillator stops, stopping the whole system, thereby considerably r educing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. stop mode can be used only when cp u is operating on the x1 input clock or ring-osc clock. halt mode can be used when cpu is operating on the x1 input clock, ring-osc clock, or subsystem cl ock. however, when the stop instruction is executed during ring- osc clock operation, the x1 oscillator st ops, but ring-osc oscillator does not stop. 2. when shifting to the stop mode, be sure to stop the peri pheral hardware operation before executing stop instruction. 3. the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) of the a/d converter mode register (adm) to 0 to stop the a/d conversi on operation, and then execute the halt or stop instruction. 4. if the ring-osc oscillator is operating before the stop mode is set, oscillation of the ring- osc clock cannot be stopped in the stop mode. however, when the ri ng-osc clock is used as the cpu clock, the cpu operation is stopped for 17/f r (s) after stop mode is released. chapter 19 standby function user?s manual u16228ej2v0ud 382 19.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . (1) oscillation stabilization time c ounter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock o scillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. reset release (reset by reset input, poc, lvi, clock moni tor, and wdt), the stop instruction, mstop (bit 7 of moc register) = 1, and mcc (bit 7 of pcc register) = 1 clear ostc to 00h. figure 19-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 1 0 0 0 0 2 11 /f x min. (204.8 s min.) 1 1 0 0 0 2 13 /f x min. (819.2 s min.) 1 1 1 0 0 2 14 /f x min. (1.64 ms min.) 1 1 1 1 0 2 15 /f x min. (3.27 ms min.) 1 1 1 1 1 2 16 /f x min. (6.55 ms min.) cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. if the stop mode is entered and th en released while the ring-osc clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only dur ing the oscillation stabilization time set by osts. therefo re, note that only the statuses during the oscillation stabilization time set by osts are set to ostc a fter stop mode has been released. 3. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by r eset input or interrupt generation. a stop mode release x1 pin voltage waveform remarks 1. values in parentheses are reference value for operation with f x = 10 mhz. 2. f x : x1 input clock oscillation frequency chapter 19 standby function user?s manual u16228ej2v0ud 383 (2) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stab ilization wait time when stop mode is released. the wait time set by osts is valid only after stop mode is released when the x1 input clock is selected as the cpu clock. after stop mode is released when the ring-osc clock is selected, check the oscillation stabilization time using ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 19-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0 0 1 2 11 /f x (204.8 s) 0 1 0 2 13 /f x (819.2 s) 0 1 1 2 14 /f x (1.64 ms) 1 0 0 2 15 /f x (3.27 ms) 1 0 1 2 16 /f x (6.55 ms) other than above setting prohibited cautions 1. if the stop mode is entered a nd then released while the ring-osc clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only dur ing the oscillation stabilization time set by osts. therefo re, note that only the statuses during the oscillation stabilization time set by osts are set to ostc a fter stop mode has been released. 2. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by r eset input or interrupt generation. a stop mode release x1 pin voltage waveform remarks 1. values in parentheses are reference value for operation with f x = 10 mhz. 2. f x : x1 input clock oscillation frequency chapter 19 standby function user?s manual u16228ej2v0ud 384 19.2 standby function operation 19.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the x1 input clo ck, ring-osc clock, or subsystem clock. the operating statuses in t he halt mode are shown below. table 19-2. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on x1 input clock when halt instruction is executed while cpu is operating on ring-osc clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation not guaranteed 16-bit timer/event counter 01 note 2 operable operation not guaranteed 8-bit timer/event counter 50 operable operati on not guaranteed when count clock other than ti50 is selected 8-bit timer/event counter 51 operable operati on not guaranteed when count clock other than ti51 is selected 8-bit timer h0 operable operation not guaranteed when count clock other than tm50 output is selected during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operation not guaranteed when count clock other than f r /2 7 is selected watch timer operable operable note 3 operable operable note 3 operable note 4 operation not guaranteed operable note 4 operation not guaranteed ring-osc cannot be stopped note 5 operable ? operable watchdog timer ring-osc can be stopped note 5 operation stopped a/d converter operable operation not guaranteed uart0 operable uart6 operable operation not guaranteed when serial clock other than tm50 output is selected during tm50 operation csi10 operable operation not guaranteed when serial clock other than external sck10 is selected serial interface csi11 note 2 operable operation not guaranteed when serial clock other than external sck11 is selected clock monitor operable operation stopped operable operation stopped multiplier/divider operable operation not guaranteed power-on-clear function note 6 operable low-voltage detection function operable external interrupt operable notes 1. when ?stopped by software? is selected for rin g-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 25 mask options ). 2. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. 3. operable when the x1 input clock is selected. 4. operation not guaranteed when other than subsystem clock is selected. 5. ?ring-osc cannot be stopped? or ?ring-osc can be stopped by softw are? can be selected by a mask option. 6. when ?poc used? is selected by a mask option. chapter 19 standby function user?s manual u16228ej2v0ud 385 table 19-2. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when ring-osc oscillation continues when ring-osc oscillation stopped note 1 system clock clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation stopped 16-bit timer/event counter 01 note 2 operable operation stopped 8-bit timer/event counter 50 operable operable onl y when ti50 is select ed as the count clock 8-bit timer/event counter 51 operable operable onl y when ti51 is select ed as the count clock 8-bit timer h0 operable operable only when tm50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operable only when the x1 input clock is selected as the count clock operable only when f r /2 7 is selected as the count clock operation stopped watch timer operable operable only wh en subsystem clo ck is selected ring-osc cannot be stopped note 3 operable ? operable ? watchdog timer ring-osc can be stopped note 3 operation stopped a/d converter operable not operable uart0 operable uart6 operable operable only when tm50 output is selected as the serial clock during tm50 operation csi10 operable operable only when external clock is selected as the serial clock serial interface csi11 note 2 operable operable only when external clock is selected as the serial clock clock monitor operable operation stopped multiplier/divider operable operation stopped power-on-clear function note 4 operable low-voltage detection function operable external interrupt operable notes 1. when ?stopped by software? is selected for rin g-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 25 mask options ). 2. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. 3. ?ring-osc cannot be stopped? or ?ring-osc can be stopped by softw are? can be selected by a mask option. 4. when ?poc used? is selected by a mask option. chapter 19 standby function user?s manual u16228ej2v0ud 386 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicin g is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 19-3. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation x1 input clock, ring-osc clock, or subsystem clock status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks chapter 19 standby function user?s manual u16228ej2v0ud 387 (b) release by reset input when the reset signal is input, halt mode is rele ased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 19-4. halt mode release by reset input (1/2) (1) when x1 input clock is used as cpu clock halt instruction reset signal x1 input clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) (2) when ring-osc clo ck is used as cpu clock halt instruction reset signal ring-osc clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency chapter 19 standby function user?s manual u16228ej2v0ud 388 figure 19-4. halt mode release by reset input (2/2) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock operating mode halt mode reset period operation stopped operating mode oscillates status of cpu (ring-osc clock) (17/f r ) subsystem clock remark f r : ring-osc clock oscillation frequency table 19-3. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset input ? ? reset processing : don?t care chapter 19 standby function user?s manual u16228ej2v0ud 389 19.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing the stop instruction, and it can be set when the cpu clock before the setting was the x1 input clock or ring-osc clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. table 19-4. operating statuses in stop mode when stop instruction is executed while cpu is operating on x1 input clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when stop instruction is executed while cpu is operating on ring- osc clock stop mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock only x1 oscillator oscillation is stopped. clock supply to the cpu is stopped. cpu operation stopped port (latch) status before st op mode was set is retained 16-bit timer/event counter 00 operation stopped 16-bit timer/event counter 01 note 2 operation stopped 8-bit timer/event counter 50 operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable only when ti51 is selected as the count clock 8-bit timer h0 operable only when tm50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable note 3 operation stopped operable note 3 watch timer operable note 4 operation stopped operable note 4 operation stopped operable note 4 operation stopped ring-osc cannot be stopped note 5 operable ? operable watchdog timer ring-osc can be stopped note 5 operation stopped a/d converter operation stopped uart0 uart6 operable only when tm50 output is selected as the serial clock during tm50 operation csi10 operable only when external sck10 is selected as the serial clock serial interface csi11 note 2 operable only when external sck11 is selected as the serial clock clock monitor operation stopped multiplier/divider operation stopped power-on-clear function note 6 operable low-voltage detection function operable external interrupt operable notes 1. when ?stopped by software? is selected for rin g-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 25 mask options ). 2. pd780133, 780134, 78f0134, 780136, 780138, and 78f0138 only. 3. operable only when f r /2 7 is selected as the count clock. 4. operable when the sub system clock is selected. 5. ?ring-osc cannot be stopped? or ?ring-osc can be stopped by softw are? can be selected by a mask option. 6. when ?poc used? is selected by a mask option. chapter 19 standby function user?s manual u16228ej2v0ud 390 (2) stop mode release figure 19-5. operation timing wh en stop mode is released ring-osc clock is selected as cpu clock when stop instruction is executed ring-osc clock x1 input clock x1 input clock is selected as cpu clock when stop instruction is executed stop mode release stop mode operation stopped (17/f r ) clock switched by software ring-osc clock x1 input clock halt status (oscillation stabilization time set by osts) x1 input clock the stop mode can be released by the following two sources. chapter 19 standby function user?s manual u16228ej2v0ud 391 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 19-6. stop mode release by interrupt request generation (1) when x1 input clock is used as cpu clock operating mode operating mode oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped x1 input clock status of cpu oscillation stabilization time (set by osts) (x1 input clock) (x1 input clock) (2) when ring-osc clo ck is used as cpu clock operating mode operating mode oscillates stop instruction stop mode standby release signal ring-osc clock status of cpu (ring-osc clock) operation stopped (17/f r ) (ring-osc clock) remarks 1. the broken lines indicate the case when the in terrupt request that has released the standby mode is acknowledged. 2. f r : ring-osc clock oscillation frequency chapter 19 standby function user?s manual u16228ej2v0ud 392 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 19-7. stop mode release by reset input (1) when x1 input clock is used as cpu clock stop instruction reset signal x1 input clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) oscillation stopped (2) when ring-osc clo ck is used as cpu clock stop instruction reset signal ring-osc clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 19-5. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset input ? ? reset processing : don?t care user?s manual u16228ej2v0ud 393 chapter 20 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by cl ock monitor x1 clock oscillation stop detection (4) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (5) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, th e watchdog timer overflow s, x1 clock oscillation stop is detected by the clock monitor, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in table 20-1. each pin is high impedan ce during reset input or during the oscillation stabilization time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and progr am execution starts using the ring- osc clock after the cpu clock operation has stopped for 17/f r (s). a reset generated by the watchdog timer and clock monitor sources is automatically released after th e reset, and program executi on starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see figures 20-2 to 20-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and program execution starts using the ring-osc clock afte r the cpu clock operation has stopped for 17/f r (s) (see chapter 22 power-on-clear circuit and chapter 23 low-voltage detector ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 input cl ock and ring-osc clock stop oscillating. 3. when the stop mode is released by a reset , the stop mode contents are held during reset input. however, the port pins become high-impedance, except fo r p130, which is set to low- level output. chapter 20 reset function user?s manual u16228ej2v0ud 394 figure 20-1. block di agram of reset function clmrf lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal clock monitor reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register chapter 20 reset function user?s manual u16228ej2v0ud 395 figure 20-2. timing of reset by reset input delay delay hi-z note normal operation cpu clock reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) reset internal reset signal port pin x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. figure 20-3. timing of reset du e to watchdog timer overflow hi-z note normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal port pin operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. caution a watchdog timer internal reset resets the watchdog timer. chapter 20 reset function user?s manual u16228ej2v0ud 396 figure 20-4. timing of reset in stop mode by reset input delay delay hi-z note normal operation cpu clock reset period (oscillation stop) reset internal reset signal port pin stop instruction execution stop status (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. remark for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 22 power- on-clear circuit and chapter 23 low-voltage detector . chapter 20 reset function user?s manual u16228ej2v0ud 397 table 20-1. hardware statuses after reset acknowledgment (1/3) hardware status after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p7, p12 to p14) (output latches) 00h (undefined only for p2) port mode registers (pm0, pm1, pm3 to pm7, pm12, pm14) ffh pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) 00h input switch control register (isc) 00h internal memory size switching register (ims) cfh internal expansion ram size sw itching register (ixs) 0ch processor clock control register (pcc) 00h ring-osc mode register (rcm) 00h main clock mode register (mcm) 00h main osc control register (moc) 00h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counters 00, 01 (tm00, tm01) 0000h capture/compare registers 000, 010, 001, 011 (cr000, cr010, cr001, cr011) 0000h mode control registers 00, 01 (tmc00, tmc01) 00h prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h 16-bit timer/event counters 00, 01 note 3 timer output control registers 00, 01 (toc00, toc01) 00h timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection regist ers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 4 00h watch timer operation m ode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h notes 1. during reset input or oscillation stabilization time wa it, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. 16-bit timer/event counter 01 is available only for the chapter 20 reset function user?s manual u16228ej2v0ud 398 table 20-1. hardware statuses after reset acknowledgment (2/3) hardware status after reset acknowledgment mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result register (adcr) undefined mode register (adm) 00h analog input channel specification register (ads) 00h power-fail comparison mode register (pfm) 00h a/d converter power-fail comparison threshold register (pft) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmis sion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh serial interface uart6 asynchronous serial interface control register 6 (asicl6) 16h transmit buffer registers 10, 11 (sotb10, sotb11) undefined serial i/o shift registers 10, 11 (sio10, sio11) undefined serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi11 note serial clock selection register s 10, 11 (csic10, csic11) 00h remainder data register 0 (sdr0) 0000h multiplication/division data regi ster a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider multiplier/divider control register 0 (dmuc0) 00h key interrupt key return mode register (krm) 00h clock monitor mode register (clm) 00h note serial interface csi11 is available only for the chapter 20 reset function user?s manual u16228ej2v0ud 399 table 20-1. hardware statuses after reset acknowledgment (3/3) hardware status after reset acknowledgment reset function reset control flag register (resf) 00h note low-voltage detection register (lvim) 00h note low-voltage detector low-voltage detection level selection register (lvis) 00h note request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh mask flag register 1h (mk1h) dfh priority specification fl ag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h note these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by clm reset by lvi resf see table 20-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) cleared (00h) held chapter 20 reset function user?s manual u16228ej2v0ud 400 20.1 register for confirming reset source many internal reset generation sources exist in the 78k0/ ke1. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc ) circuit, and reading resf clear resf to 00h. figure 20-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 clmrf lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. clmrf internal reset req uest by clock monitor (clm) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 20-2. table 20-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by clm reset by lvi wdtrf set (1) held held clmrf held set (1) held lvirf cleared (0) cleared (0) held held set (1) user?s manual u16228ej2v0ud 401 chapter 21 clock monitor 21.1 functions of clock monitor the clock monitor samples the x1 input clock using the on-chip ring-osc, and generates an internal reset signal when the x1 input clock is stopped. when a reset signal is generated by the clock monitor, bit 1 (clmrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 20 reset function . the clock monitor automatically stops under the following conditions. ? reset is released and during the oscillation stabilization time ? in stop mode and during the oscillation stabilization time ? when the x1 input clock is stopped by software (mstop = 1 or mcc = 1) and during the oscillation stabilization time ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) 21.2 configuration of clock monitor the clock monitor includes the following hardware. table 21-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 21-1. block diag ram of clock monitor operation mode controller x1 input clock ring-osc clock clme clock monitor mode register (clm) internal bus x1 oscillation monitor circuit internal reset signal x1 oscillation control signal (mcc, mstop) x1 oscillation stabilization status (ostc overflow) remark mcc: bit 7 of the processor clock control register (pcc) mstop: bit 7 of the main osc control register (moc) ostc: oscillation stabilization time counter status register (ostc) chapter 21 clock monitor user?s manual u16228ej2v0ud 402 21.3 registers controlling clock monitor the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register sets the operation mode of the clock monitor. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 21-2. format of clock monitor mode register (clm) 7 0 clme 0 1 symbol clm address: ffa9h after reset: 00h r/w 6 0 disables clock monitor operation enables clock monitor operation 5 0 4 0 3 0 enables/disables clock monitor operation 2 0 1 0 <0> clme cautions 1. once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by re set input or the internal reset signal. 2. if the reset signal is generated by the clock monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control flag regi ster (resf) is set to 1. chapter 21 clock monitor user?s manual u16228ej2v0ud 403 21.4 operation of clock monitor this section explains the functions of the clock monitor. the monitor star t and stop conditions are as follows. chapter 21 clock monitor user?s manual u16228ej2v0ud 404 figure 21-3. timing of clock monitor (1/4) (1) when internal reset is executed by oscillation stop of x1 input clock 4 clocks of ring-osc clock x1 input clock ring-osc clock internal reset signal clme clmrf (2) clock monitor status after reset input (clme = 1 is set after reset input and during x1 input clock oscillation stabilization time) cpu operation clock monitor status clme ring-osc clock x1 input clock reset oscillation stopped oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring waiting for end of oscillation stabilization time oscillation stopped 17 clocks set to 1 by software reset reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. even if clme is set to 1 by software during the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is not performed un til the oscillation stabilizat ion time of the x1 input clock ends. monitoring is automatically started at the end of the oscillation stabilization time. chapter 21 clock monitor user?s manual u16228ej2v0ud 405 figure 21-3. timing of clock monitor (2/4) (3) clock monitor status after reset input (clme = 1 is set after reset input and at the e nd of x1 input clock oscillation stabilization time) cpu operation clock monitor status clme reset ring-osc clock x1 input clock reset oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring 17 clocks set to 1 by software reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. when clme is set to 1 by software at the end of the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is started. (4) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on x1 input clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring clme ring-osc clock x1 input clock (cpu clock) cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (time set by osts register) when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. chapter 21 clock monitor user?s manual u16228ej2v0ud 406 figure 21-3. timing of clock monitor (3/4) (5) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on ri ng-osc clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring stopped monitoring clme ring-osc clock (cpu clock) x1 input clock cpu operation normal operation 17 clocks clock supply stopped normal operation oscillation stopped oscillation stabilization time (time set by osts register) stop when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. (6) clock monitor status after x1 input clock oscillation is stopped by software clock monitor status clme mstop or mcc note ring-osc clock x1 input clock oscillation stabilization time (time set by osts register) normal operation (ring-osc clock or subsystem clock note ) monitoring monitoring stopped monitoring cpu operation monitoring stopped oscillation stopped when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the x1 input clock is stopped, monitoring automatical ly starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped when oscillation of the x1 input clo ck is stopped and during the osc illation stabilization time. note the register that controls oscillati on of the x1 input clock differs depen ding on the type of the clock supplied to the cpu. ? when cpu operates on ring-osc clock: controlled by bit 7 (mstop) of the main osc control register (moc) ? when cpu operates on subsystem clock: controlled by bit 7 (mcc) of the processor clock control register (pcc) chapter 21 clock monitor user?s manual u16228ej2v0ud 407 figure 21-3. timing of clock monitor (4/4) (7) clock monitor status after ring-osc clock oscillation is stopped by software ring-osc clock x1 input clock cpu operation normal operation (x1 input clock or subsystem clock) oscillation stopped rstop note clock monitor status monitoring monitoring stopped monitoring clme when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the ring-osc clock is stopped, monitoring automatically starts afte r the ring-osc clock is stopped. monitoring is stopped when oscillation of the ring-osc clock is stopped. note if it is specified by a mask option that ring-osc cannot be stopped, the setting of bit 0 (rstop) of the ring-osc mode register (rcm) is invalid. to set rsto p, be sure to confirm that bit 1 (mcs) of the main clock mode register (mcm) is 1. user?s manual u16228ej2v0ud 408 chapter 22 power-on-clear circuit 22.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? ? ? ? ? ? chapter 22 power-on-clear circuit user?s manual u16228ej2v0ud 409 22.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 22-1. figure 22-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc ) internal reset signal v dd v dd mask option 22.3 operation of power-on-clear circuit in the power-on-clear circuit, the supply voltage (v dd ) and detection voltage (v poc ) are compared, and when v dd < v poc , an internal reset signal is generated. figure 22-2. timing of internal reset si gnal generation in powe r-on-clear circuit time supply voltage (v dd ) poc detection voltage (v poc ) 2.7 v internal reset signal chapter 22 power-on-clear circuit user?s manual u16228ej2v0ud 410 22.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 22 power-on-clear circuit user?s manual u16228ej2v0ud 411 figure 22-3. example of software pr ocessing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no no wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes yes user?s manual u16228ej2v0ud 412 chapter 23 low-voltage detector 23.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? ? ? ? ? chapter 23 low-voltage detector user?s manual u16228ej2v0ud 413 23.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) chapter 23 low-voltage detector user?s manual u16228ej2v0ud 414 (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears lvim to 00h. figure 23-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd 2 0 3 0 <4> lvie 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h r/w note 1 lvion notes 2, 3 enables low-voltage detection operation 0 disables operation 1 enables operation lvie notes 2, 4, 5 specifies reference voltage generator 0 disables operation 1 enables operation lvimd note 2 low-voltage detection operation mode selection 0 generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 6 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. bit 0 is read-only. 2. lvion, lvie, and lvimd are cleared to 0 at a reset other than an lvi reset. these are not cleared to 0 at an lvi reset. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 4. if ?poc cannot be used? is selected by a mask opti on, wait for 2 ms or more by software from when lvie is set to 1 until lvion is set to 1. 5. if ?poc used? is selected by a mask option, se tting of lvie is invalid because the reference voltage generator in the lvi circuit always operates. 6. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. caution to stop lvi, follow either of the procedures below. ? when using 8-bit manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instru ction: clear lvion to 0 first and then clear lvie to 0. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 415 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. reset input clears lvis to 00h. figure 23-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 0 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis2 lvis1 lvis0 detection level 0 0 0 v lvi0 (4.3 v 0.2 v) 0 0 1 v lvi1 (4.1 v 0.2 v) 0 1 0 v lvi2 (3.9 v 0.2 v) 0 1 1 v lvi3 (3.7 v 0.2 v) 1 0 0 v lvi4 (3.5 v 0.2 v) note 1 1 0 1 v lvi5 (3.3 v 0.15 v) notes 1, 2 1 1 0 v lvi6 (3.1 v 0.15 v) notes 1, 2 1 1 1 setting prohibited notes 1. when the detection voltage of the poc circuit is specified as v poc = 3.5 v 0.2 v by a mask option, do not select v lvi4 to v lvi6 as the lvi detection voltage. even if v lvi4 to v lvi6 are selected, the poc circuit has priority. 2. this setting is prohibited in (a1) grade products and (a2) grade products. caution be sure to clea r bits 3 to 7 to 0. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 416 23.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection regist er (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> wait until it is checked that (supply voltage (v dd ) > detection voltage (v lvi )) by bit 0 (lvif) of lvim. <8> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 23-4 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. 2. if ?poc used? is selected by a mask opt ion, procedures <3> and <4> are not required. 3. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0, lvion to 0, and lvie to 0 in that order. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 417 figure 23-4. timing of low-voltage dete ctor internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared not cleared not cleared cleared by software <2> <1> note 1 <5> <7> <8> time clear clear clear clear <3> <4> 2 ms or longer <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) lvimd flag (set by software) notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag register (resf). for details of resf, see chapter 20 reset function . remark <1> to <8> in figure 23-4 above correspond to <1> to <8> in the description of ?when starting operation? in 23.4 (1) when used as reset . chapter 23 low-voltage detector user?s manual u16228ej2v0ud 418 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection regist er (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> confirm that ?supply voltage (v dd ) > detection voltage (v lvi )? at bit 0 (lvif) of lvim. <8> clear the interrupt request flag of lvi (lviif) to 0. <9> release the interrupt mask flag of lvi (lvimk). <10> execute the ei instruction (w hen vector interrupts are used). figure 23-5 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. caution if ?use poc? is selected by a mask opt ion, procedures <3> and <4> are not required. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0 first, and then clear lvie to 0. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 419 figure 23-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v time lvif flag intlvi lviif flag internal reset signal <2> <1> note 1 <5> <7> <8> cleared by software <3> <4> 2 ms or longer <9> cleared by software <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) note 2 note 2 notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif and lviif flags may be set (1). remark <1> to <9> in figure 23-5 above correspond to <1> to <9> in the description of ?when starting operation? in 23.4 (2) when used as interrupt . chapter 23 low-voltage detector user?s manual u16228ej2v0ud 420 23.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (2) below. in this system, take the following actions. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 421 figure 23-6. example of software pr ocessing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage yes lvi ; the ring-osc clock is set as the cpu clock when the reset signal is generated ; the cause of reset (power-on-clear, wdt, lvi, or clock monitor) can be identified by the resf register. ; change the cpu clock from the ring-osc clock to the x1 input clock. ; check the stabilization of oscillation of the x1 input clock by using the ostc register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the ring-osc clock. source: f r (480 khz (max.))/2 7 compare value 200 = 53 ms (f r : ring-osc clock oscillation frequency) no note 1 reset checking cause of reset note 2 check stabilization of oscillation change cpu clock 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period , initialization processing is not started. 2. a flowchart is shown on the next page. chapter 23 low-voltage detector user?s manual u16228ej2v0ud 422 figure 23-6. example of software pr ocessing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no yes wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes no (2) when used as interrupt check that ?supply voltage (v dd ) > detection voltage (v lvi )? in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltage detection register (lvim). clear bit 0 (lviif) of interrupt request flag register 0l (if0l) to 0 and enable interrupts (ei). in a system where the supply voltage fluc tuation period is long in the vicinity of the lvi detection voltage, wait for the supply voltage fluctuation peri od, check that ?supply voltage (v dd ) > detection voltage (v lvi )? using the lvif flag, and then enable interrupts (ei). user?s manual u16228ej2v0ud 423 chapter 24 regulator 24.1 outline of regulator the 78k0/ke1 includes a circuit to realize constant-volta ge operation inside the device. to stabilize the regulator output voltage, connect the regc pin to v ss via a capacitor (1 ? ? ? ? ? chapter 24 regulator user?s manual u16228ej2v0ud 424 figure 24-2. regc pin connection (a) when regc = v dd reg input voltage = 2.7 to 5.5 v voltage supply to oscillator/internal logic = 2.7 to 5.5 v v dd regc (b) when connecting regc pin to v ss via a capacitor reg input voltage = 4.0 to 5.5 v voltage supply to oscillator/internal logic = 3.5 v v dd regc 1 f (recommended) user?s manual u16228ej2v0ud 425 chapter 25 mask options mask rom versions are provided with the following mask options. 1. power-on-clear (poc) circuit ? ? ? ? ? ? user?s manual u16228ej2v0ud 426 chapter 26 rom correction 26.1 functions of rom correction the chapter 26 rom correction user?s manual u16228ej2v0ud 427 (1) correction address registers 0 and 1 (corad0, corad1) these registers set the start address (correction address) of the instruction(s) to be corrected in the mask rom or flash memory. the rom correction corrects two places (max.) of the pr ogram. addresses are set to two registers, corad0 and corad1. if only one place needs to be corrected, set the address to either of the registers. corad0 and corad1 are set by a 16-bit memory manipulation instruction. reset input clears corad0 and corad1 to 0000h. figure 26-2. format of correction address registers 0 and 1 ff3ah/ff3bh 0000h symbol 15 corad0 0 address ff38h/ff39h after reset 0000h r/w r/w corad1 r/w cautions 1. set the corad0 and corad1 when bit 1 (coren0) and bit 3 (coren1) of the correction control register (corcn: see figure 26-3) are 0. 2. only addresses where operation codes are st ored can be set in corad0 and corad1. 3. do not set the following addresses to corad0 and corad1. ? address value in table area of table refere nce instruction (callt instruction): 0040h to 007fh ? address value in vector table area: 0000h to 003fh (2) comparator the comparator always compares the correction addres s value set in correction address registers 0 and 1 (corad0, corad1) with the fetch address value. when bit 1 (coren0) or bit 3 (coren1) of the correction control register (corcn) is 1 and the correction addr ess matches the fetch address value, the correction branch request signal (br !f7fdh) is generat ed from the rom correction circuit. chapter 26 rom correction user?s manual u16228ej2v0ud 428 26.3 register controlling rom correction the rom correction is controlled by the co rrection control register (corcn). (1) correction control register (corcn) this register controls whether or not the correction branch request si gnal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. the correction control register consists of correction enable flags (coren0, coren1) and correction status flags (corst0, corst1). the correction enable flags enable or disable the comparator match detection signal, and correction status flags show the values are matched. corcn is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears corcn to 00h. clear corst0 and corst1 using software. figure 26-3. format of correction control register 7 0 6 0 5 0 4 0 coren1 corst1 coren0 corst0 symbol corcn address ff8ah after reset coren0 0 1 corst0 0 1 coren1 0 1 corst1 0 1 r/w r/w note 00h correction address register 0 and fetch address match detection not detected detected correction address register 0 and fetch address match detection control disabled enabled correction address register 1 and fetch address match detection not detected detected correction address register 1 and fetch address match detection control disabled enabled <3> <2> <1> <0> note do not set bits 0 and 2 to 1. chapter 26 rom correction user?s manual u16228ej2v0ud 429 26.4 rom correction usage example the example of rom correction when the instruction at address 1000h ?add a, #1? is changed to ?add a, #2? is as follows. figure 26-4. rom correction usage example add a, #2 br !1002h br !f702h add a, #1 mov b, a 0000h 0080h program start 1000h 1002h internal rom or internal flash memory internal expansion ram f400h f702h f7fdh f7ffh (1) (2) (3) efffh (1) branches to address f7fdh when the preset value 10 00h in the correction address register matches the fetch address value after the main program is started. (2) branches to any address (address f702h in this exam ple) by setting the entire-s pace branch instruction (br !addr16) to address f7fdh with the main program. (3) returns to the internal rom (int ernal flash memory) program after execut ing the substitute instruction add a, #2. chapter 26 rom correction user?s manual u16228ej2v0ud 430 26.5 rom correction application how to apply the example shown in 26.4 is described below. (1) store the correction address and instruction after corre ction (patch program) to nonvolatile memory (such as eeprom tm ) outside the microcontroller. when two places should be corrected, store the branch destination judgment prog ram as well. the branch destination judgment program checks which one of the addresses set to correction address registers 0 and 1 (corad0 or corad1) generates the correction branch. figure 26-5. example of storing to eeprom (when one place is corrected) ra78k/0 eeprom source program 00 10 0d 02 9b 02 10 00h 01h 02h ffh cseg at 0000h dw #1000h add a, #2 br !1002h chapter 26 rom correction user?s manual u16228ej2v0ud 431 (2) assemble in advance the initial setting routine as shown in figure 26-6 to correct the program. figure 26-6. initial setting routine no yes initial setting load the contents of external nonvolatile memory into internal expansion ram correction address register setting rom correction operation enabled is rom correction used ? note rom correction main program note whether the rom correction is used or not should be jud ged by the port input level. for example, when the p20 input level is high, the rom correction is used, otherwise, it is not used. (3) after reset, store the corrected address and program that have been previously stored in the external nonvolatile memory with initial setting routine for rom corr ection of the user to internal expansion ram (see figure 26-6 ). set the start address of the instruction to be co rrected to corad0 and corad1, and set bits 1 and 3 (coren0, coren1) of the correction c ontrol register (corcn) to 1. (4) set the main program so that the program branches fr om the specified address of the internal expansion ram (f7fdh) to the internal expansion ram address where the corrected program is stored using the entire space branch instruction (br !addr16). (5) after the main program is star ted, the fetch address value and the va lues set in corad0 and corad1 are always compared by the comparator in the rom correction circuit. when these values match, the correction branch request signal is generated. simultaneously th e corresponding correction status flag (corst0 or corst1) is set to 1. (6) branch to the address f7fdh by the correction branch request signal. (7) branch to the internal expansion ram address set in (4 ) by the entire-space branch instruction of the address f7fdh. (8) when one place is corrected, the correction progra m is executed. when two places are corrected, the correction status flag is checked with the branch destination judgment progra m, and branches to the correction program. chapter 26 rom correction user?s manual u16228ej2v0ud 432 figure 26-7. rom correction operation no yes internal rom (internal flash memory) program start does fetch address match with correction address? set correction status flag correction branch (branch to address f7fdh) correction program execution rom correction chapter 26 rom correction user?s manual u16228ej2v0ud 433 26.6 program execution flow figures 26-8 and 26-9 show the program transition diagrams when the rom correction is used. figure 26-8. program transition di agram (when one place is corrected) correction place internal rom internal rom (internal flash memory) jump ffffh f7ffh f7fdh xxxxh 0000h (1) (2) (3) br !jump correction program (1) branches to address f7fdh when fetch address matches correction address (2) branches to correction program (3) returns to internal rom (internal flash memory) program remark area filled with diagonal lines: internal expansion ram jump: correction program start address chapter 26 rom correction user?s manual u16228ej2v0ud 434 figure 26-9. program transition di agram (when two places are corrected) internal rom (internal flash memory) correction place 1 internal rom (internal flash memory) jump internal rom (internal flash memory) (1) (2) (3) (4) (5) (6) (7) (8) ffffh f7ffh f7fdh yyyyh xxxxh 0000h br !jump branch destination judgment program correction program 2 correction program 1 correction place 2 (1) branches to address f7fdh when fetch address matches correction address (2) branches to branch destination judgment program (3) branches to correction program 1 by branch des tination judgment program (btclr !corst0, $xxxxh) (4) returns to internal rom (internal flash memory) program (5) branches to address f7fdh when fetch address matches correction address (6) branches to branch destination judgment program (7) branches to correction program 2 by branch des tination judgment program (btclr !corst1, $yyyyh) (8) returns to internal rom (internal flash memory) program remark area filled with diagonal lines: internal expansion ram jump: branch destination judgment program start address chapter 26 rom correction user?s manual u16228ej2v0ud 435 26.7 cautions for rom correction (1) address values set in correction address registers 0 and 1 (corad0, corad1) must be addresses where instruction codes are stored. (2) correction address registers 0 and 1 (corad0, co rad1) should be set when the correction enable flag (coren0, coren1) is 0 (when the correction branch is in disabled state). if address is set to corad0 or corad1 when coren0 or coren1 is 1 (when the corr ection branch is in enabled state), the correction branch may start with the different addr ess from the set address value. (3) do not set the address value of instruction immediately after the instruction that sets the correction enable flag (coren0, coren1) to 1, to correction address regist er 0 or 1 (corad0, cora d1); the correction branch may not start. (4) do not set the address value in table area of table re ference instruction (callt instruction) (0040h to 007fh), and the address value in vector table area (0000h to 003fh) to correction address registers 0 and 1 (corad0, corad1). (5) do not set two addresses immediately after the instru ctions shown below to correction address registers 0 and 1 (corad0, corad1). (that is, w hen the mapped terminal address of these instructions is n, do not set the address values of n + 1 and n + 2.) ? ret ? reti ? retb ? br $addr16 ? stop ? halt user?s manual u16228ej2v0ud 436 chapter 27 pd78f0134, 78f0138 the pd78f0134 and 78f0138 are provided as the flash memory version of the 78k0/ke1. the pd78f0134 and 78f0138 replace the internal mask rom of the pd780134 and 780138 respectively with flash memory to which a program can be written, erased, and overwritten while mounted on the board. table 27-1 lists the differences between the pd78f0134, 78f0138 and the mask rom versions. table 27-1. differences between pd78f0134, 78f0138 and mask rom versions item pd78f0134, 78f0138 mask rom versions internal rom configurati on flash memory mask rom internal rom capacity pd78f0134 note 1 : 32 kb note 2 pd78f0138: 60 kb note 2 pd780131: 8 kb pd780132: 16 kb pd780133: 24 kb pd780134: 32 kb pd780136: 48 kb pd780138: 60 kb internal high-speed ram capacity pd78f0134 note 1 : 1024 bytes note 2 pd78f0138: 1024 bytes note 2 pd780131: 512 bytes pd780132: 512 bytes pd780133: 1024 bytes pd780134: 1024 bytes pd780136: 1024 bytes pd780138: 1024 bytes internal expansion ram capacity pd78f0134 note 1 : none pd78f0138: 1024 bytes note 2 pd780131: none pd780132: none pd780133: none pd780134: none pd780136: 1024 bytes pd780138: 1024 bytes ic pin none available v pp pin available none electrical s pecifications, recommended soldering conditions refer to the description of electrical specifications and recommended soldering conditions. notes 1. the pd78f0134 does not support the pd780136 and 780138. 2. the same capacity as the mask rom versions can be specified by means of the internal memory size switching register (ims) and the internal ex pansion ram size switching register (ixs). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre- producing an application set wit h the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions. chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 437 27.1 internal memory size switching register the pd78f0134 and 78f0138 allow users to sele ct the internal memory capacity using the internal memory size switching register (ims) so that the sa me memory map as that of the mask rom versions with a different internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. cautions 1. be sure to set the value of th e relevant mask rom versi on at initialization. 2. the pd78f0134 does not support the pd780136 and 780138. figure 27-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal hi gh-speed ram capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 0 0 1 0 8 kb 0 1 0 0 16 kb 0 1 1 0 24 kb 1 0 0 0 32 kb 1 1 0 0 48 kb 1 1 1 1 60 kb other than above setting prohibited the ims settings required to obtain the same memory ma p as mask rom versions are shown in table 27-2. table 27-2. internal memory si ze switching register settings target mask rom versions ims setting pd780131 42h pd780132 44h pd780133 c6h pd780134 c8h pd780136 cch pd780138 cfh cautions 1. when using a mask rom version, be sure to set the value indicated in table 27-2 to ims. 2. the pd78f0134 does not support the pd780136 and 780138. chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 438 27.2 internal expansion ram size switching register this register is used to set the internal expansion ram capacity via software. this register is set by an 8-bit memory manipulation instruction. reset input sets ixs to 0ch. cautions 1. be sure to set the value of th e relevant mask rom versi on at initialization. 2. the pd78f0134 does not support the pd780136 and 780138. figure 27-2. format of internal expans ion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 7 6 5 4 3 2 1 0 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 0 1 1 0 0 0 bytes 0 1 0 1 0 1024 bytes other than above setting prohibited the ixs settings required to obtain the same memory ma p as mask rom versions are shown in table 27-3. table 27-3. internal expansion ram size switching register settings target mask rom versions ixs setting pd780131 0ch pd780132 0ch pd780133 0ch pd780134 0ch pd780136 0ah pd780138 0ah cautions 1. when using a mask rom version, be sure to set the value indicated in table 27-3 to ixs. 2. the pd78f0134 does not support the pd780136 and 780138. chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 439 27.3 writing with flash programmer data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) on-board programming the contents of the flash memory can be rewritten after the pd78f0134 or 78f0138 has been mounted on the target system. the connectors that connect the d edicated flash programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicated program adapter (fa series) before the pd78f0134 or 78f0138 is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 27-4. wiring between pd78f0134 or 78f0138 and dedicated flash programmer (1/2) (1) 3-wire serial i/o (csi10) pin configuration of dedicated flash pr ogrammer with csi10 with csi10 + hs signal name i/o pin function pin name pin no. pin name pin no. si/rxd input receive signal so10/p12 25 so10/p12 25 so/txd output transmit signal si10/rxd0/p11 26 si10/rxd0/p11 26 sck output transfer clock sck10/txd0/p10 27 sck10/txd0/p10 27 x1 7 x1 7 clk output clock to pd78f0134 or 78f0138 x2 note 1 8 x2 note 1 8 /reset output reset signal reset 9 reset 9 v pp output write voltage v pp 3 v pp 3 h/s input handshake signal not needed not needed hs/p15/toh0 22 v dd 4 v dd 4 ev dd 33 ev dd 33 v dd i/o v dd voltage generation/voltage monitor note 2 av ref 1 av ref 1 v ss 6 v ss 6 ev ss 32 ev ss 32 gnd ? ground av ss 2 av ss 2 notes 1. when using the clock out of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2. 2. flashpro iii only cautions 1. be sure to connect the re gc pin in either of the following ways. ? to gnd via a 1 f capacitor ? directly to v dd 2. when connecting the regc pin to gnd via a 1 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. create an oscillator on th e board to supply a clock. chapter 27 ? ? ? chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 441 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 27-3. example of wiring ad apter for flash memory writing in 3-wire serial i/o (csi10) mode gnd vdd vdd2 (lvdd) si so sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) note 1 gnd 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5 note 2 notes 1. pd78f0134, 78f0138, 78f0134(a) , 78f0138(a): 2.7 to 5.5 v pd78f0134(a1), 78f0138(a1): 3.3 to 5.5 v 2. connect the regc pin as follows. pd78f0134, 78f0138, 78f 0134(a), 78f0138(a): connect directly to v dd or connect to gnd via a 1 f capacitor pd78f0134(a1), 78f0138(a1): connect directly to v dd chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 442 figure 27-4. example of wiring adap ter for flash memory writing in 3- wire serial i/o (csi10 + hs) mode gnd vdd si so sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) note 1 gnd 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) 5 note 2 notes 1. pd78f0134, 78f0138, 78f0134(a) , 78f0138(a): 2.7 to 5.5 v pd78f0134(a1), 78f0138(a1): 3.3 to 5.5 v 2. connect the regc pin as follows. pd78f0134, 78f0138, 78f 0134(a), 78f0138(a): connect directly to v dd or connect to gnd via a 1 f capacitor pd78f0134(a1), 78f0138(a1): connect directly to v dd chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 443 figure 27-5. example of wiri ng adapter for flash memory wr iting in uart (uart0) mode gnd vdd si so sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) note 1 gnd 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) 5 note 2 notes 1. pd78f0134, 78f0138, 78f0134(a) , 78f0138(a): 2.7 to 5.5 v pd78f0134(a1), 78f0138(a1): 3.3 to 5.5 v 2. connect the regc pin as follows. pd78f0134, 78f0138, 78f 0134(a), 78f0138(a): connect directly to v dd or connect to gnd via a 1 f capacitor pd78f0134(a1), 78f0138(a1): connect directly to v dd chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 444 figure 27-6. example of wiring adapter for flash memory writin g in uart (uart0 + hs) mode gnd vdd si so sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) note 1 gnd 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) 5 note 2 notes 1. pd78f0134, 78f0138, 78f0134(a) , 78f0138(a): 2.7 to 5.5 v pd78f0134(a1), 78f0138(a1): 3.3 to 5.5 v 2. connect the regc pin as follows. pd78f0134, 78f0138, 78f 0134(a), 78f0138(a): connect directly to v dd or connect to gnd via a 1 f capacitor pd78f0134(a1), 78f0138(a1): connect directly to v dd chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 445 figure 27-7. example of wiri ng adapter for flash memory wr iting in uart (uart6) mode gnd vdd si so sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) note 1 gnd 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) 5 note 2 notes 1. pd78f0134, 78f0138, 78f0134(a) , 78f0138(a): 2.7 to 5.5 v pd78f0134(a1), 78f0138(a1): 3.3 to 5.5 v 2. connect the regc pin as follows. pd78f0134, 78f0138, 78f 0134(a), 78f0138(a): connect directly to v dd or connect to gnd via a 1 f capacitor pd78f0134(a1), 78f0138(a1): connect directly to v dd chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 446 27.4 programming environment the environment required for writing a program to the flash memory of the pd78f0134 and 78f0138 is illustrated below. figure 27-8. environment for wr iting program to flash memory rs-232c host machine pd78f0134, 78f0138 v pp v dd v ss reset csi10/uart0/uart6 dedicated flash programmer usb note pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve note flashpro iv only a host machine that controls the dedic ated flash programmer is necessary. to interface between the dedic ated flash programmer and the pd78f0134 or 78f0138, cs i10, uart0, or uart6 is used for manipulation such as writing and erasi ng. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 27.5 communication mode communication between the dedicated flash programmer and the pd78f0134 or 78f0138 is established by serial communication via csi10, uart0, or uart6 of the pd78f0134 or 78f0138. (1) csi10 transfer rate: 200 khz to 2 mhz figure 27-9. communication with de dicated flash programmer (csi10) pd78f0134, 78f0138 v pp v dd /ev dd /av ref v ss /ev ss /av ss reset so10 si10 sck10 v pp v dd gnd /reset si/rxd so/txd x1 clk x2 sck dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xx xxx xxxxxx xxxx xxxx yyyy statve chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 447 (2) csi communication m ode supporting handshake transfer rate: 200 khz to 2 mhz figure 27-10. communication with dedi cated flash programmer (csi10 + hs) pd78f0134, 78f0138 v pp reset so10 si10 sck10 hs v pp v dd gnd /reset si/rxd so/txd sck x1 clk x2 h/s dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y xxxxx xxxxxx xxxx x x x x y y y y statve v dd /ev dd /av ref v ss /ev ss /av ss (3) uart0 transfer rate: 4800 to 38400 bps figure 27-11. communication with de dicated flash programmer (uart0) pd78f0134, 78f0138 v pp reset txd0 x1 v pp v dd gnd /reset si/rxd rxd0 so/txd clk x2 dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve v dd /ev dd /av ref v ss /ev ss /av ss (4) uart communication mo de supporting handshake transfer rate: 4800 to 38400 bps figure 27-12. communication with dedi cated flash programmer (uart0 + hs) pd78f0134, 78f0138 v pp reset txd0 rxd0 hs v pp v dd gnd /reset si/rxd so/txd x1 clk x2 h/s dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve v dd /ev dd /av ref v ss /ev ss /av ss chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 448 (5) uart6 transfer rate: 4800 to 76800 bps figure 27-13. communication with de dicated flash programmer (uart6) pd78f0134, 78f0138 v pp v dd v ss reset txd6 rxd6 v pp v dd gnd /reset si/rxd so/txd x1 clk x2 dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y yy xxxxx xxxxxx xxxx x x x x y y y y statve if flashpro iii/flashpro iv is used as the dedicated flas h programmer, flashpro iii/flashpro iv generates the following signal for the pd78f0134 or 78f0138. for details, refer to the flashpro iii/flashpro iv manual. table 27-5. pin connection flashpro iii/flashpro iv pd78f0134, 78f0138 connection signal name i/o pin function pin name csi00 uart0 uart6 v pp output write voltage v pp v dd i/o v dd voltage generation/voltage monitor note 1 v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output to pd78f0134/78f0138 x1, x2 note 2 { { { /reset output reset signal reset si/rxd input receive signal so10/txd0/txd6 so/txd output transmit signal si10/rxd0/rxd6 sck output transfer clock sck10 h/s input handshake signal hs notes 1. flashpro iii only 2. for off-board writing only: connect the clock output of the flash programmer to x1 and its inverse signal to x2. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. : in handshake mode chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 449 27.6 handling of pins on board to write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. first provide a function that select s the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 27.6.1 v pp pin in the normal operation mode, the v pp pin is connected to v ss . in addition, a write voltage of 10.0 v (typ.) is supplied to the v pp pin in the flash memory programming mode. perform the following pin handling. (1) connect pull-down resistor r vpp = 10 k ? to the v pp pin. (2) switch the input of the v pp pin to the programmer side by using a ju mper on the board or to gnd directly. figure 27-14. example of connection of v pp pin pd78f0134, 78f0138 v pp dedicated flash programmer connection pin pull-down resistor (r vpp ) 27.6.2 serial interface pins the pins used by each serial interface are listed below. table 27-6. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 csi10 + hs so10, si10, sck10, hs/p15 uart0 txd0, rxd0 uart0 + hs txd0, rxd0, hs/p15 uart6 txd6, rxd6 to connect the dedicated flash programmer to the pins of a serial interface that is co nnected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. chapter 27 chapter 27 ? ? chapter 27 pd78f0134, 78f0138 user?s manual u16228ej2v0ud 452 27.7 programming method 27.7.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 27-18. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes v pp pulse supply no end flash memory programming mode is set 27.7.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash programmer, set the pd78f0134 or 78f0138 in the flash memory programming mode. to set the mode, set the v pp pin and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 27-19. flash memory programming mode 10.0 v v ss reset v pp v dd v pp pulse flash memory programming mode 12 n v pp operation mode v ss normal operation mode 10.0 v flash memory programming mode chapter 27 chapter 27 user?s manual u16228ej2v0ud 455 chapter 28 instruction set this chapter lists each instruction set of the 78k0/ke1 in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instruction user?s manual (u12326e) . 28.1 conventions used in operation list 28.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in ac cordance with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. upper case letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 28-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, refer to table 3-6 special function register list . chapter 28 instruction set user?s manual u16228ej2v0ud 456 28.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 28.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored chapter 28 instruction set user?s manual u16228ej2v0ud 457 28.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) mov [hl + c], a 1 6 7 + m (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. 4. m is the number of waits when the exte rnal memory expansion area is written. chapter 28 instruction set user?s manual u16228ej2v0ud 458 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 + 2n ax (addr16) movw !addr16, ax 3 10 12 + 2m (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) add a, [hl + c] 2 8 9 + n a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + c a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. 4. m is the number of waits when the exte rnal memory expansion area is written. chapter 28 instruction set user?s manual u16228ej2v0ud 459 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 + n a, cy a ? (addr16) a, [hl] 1 4 5 + n a, cy a ? (hl) a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 + n a, cy a ? (addr16) ? cy a, [hl] 1 4 5 + n a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a [hl] a, [hl + byte] 2 8 9 + n a a [hl + byte] a, [hl + b] 2 8 9 + n a a [hl + b] 8-bit operation and a, [hl + c] 2 8 9 + n a a [hl + c] notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. chapter 28 instruction set user?s manual u16228ej2v0ud 460 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) or a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) xor a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 + n a ? (addr16) a, [hl] 1 4 5 + n a ? (hl) a, [hl + byte] 2 8 9 + n a ? (hl + byte) a, [hl + b] 2 8 9 + n a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 + n a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. chapter 28 instruction set user?s manual u16228ej2v0ud 461 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. 4. m is the number of waits when the exte rnal memory expansion area is written. chapter 28 instruction set user?s manual u16228ej2v0ud 462 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 + n + m (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. 4. m is the number of waits when the exte rnal memory expansion area is written. chapter 28 instruction set user?s manual u16228ej2v0ud 463 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 28 instruction set user?s manual u16228ej2v0ud 464 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1(enable interrupt) di 2 ? 6 ie 0(disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the exte rnal memory expansion area is read. 4. m is the number of waits when the exte rnal memory expansion area is written. chapter 28 instruction set user?s manual u16228ej2v0ud 465 28.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a? chapter 28 instruction set user?s manual u16228ej2v0ud 466 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 chapter 28 instruction set user?s manual u16228ej2v0ud 467 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop user?s manual u16228ej2v0ud 468 chapter 29 electrical specifications (standard products, (a) grade products) target products: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 469 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 20 ma per pin p60 to p63 30 ma p00 to p06, p40 to p43, p50 to p53, p70 to p77 35 ma output current, low i ol total of all pins 70 ma p10 to p17, p30 to p33, p60 to p63, p120, p130, p140, p141 35 ma in normal operation mode ? 40 to +85 operating ambient temperature t a in flash memory programming mode ? 10 to +85 c mask rom version ? 65 to +150 storage temperature t stg flash memory version ? 40 to +125 c notes 1. must be 6.5 v or lower. 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (15 s if the supply voltage is dropped by t he regulator) (see a in the figure below). ? when supply voltage drops raise v dd 10 s or more after v pp falls below the lower-limit value (2 .7 v) of the operating voltage range of v dd (see b in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 470 x1 oscillator characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit when a capacitor is connected to the regc pin note 2 4.0 v v dd 5.5 v 2.0 8.38 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 ceramic resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 1 when the regc pin is directly connected to v dd 2.7 v v dd < 3.3 v 2.0 5.0 mhz when a capacitor is connected to the regc pin note 2 4.0 v v dd 5.5 v 2.0 8.38 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 crystal resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 1 when the regc pin is directly connected to v dd 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 x1 input frequency (f xp ) note 1 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 46 500 3.3 v v dd < 4.0 v 56 500 external clock note 3 x2 x1 x1 input high- /low-level width (t xph , t xpl ) 2.7 v v dd < 3.3 v 96 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. when the regc pin is connected to v ss via a capacitor (1 f: recommended). 3. connect the regc pin directly to v dd . cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc afte r reset, check the oscillation stabilization time of the x1 input clock using the oscillation stabilizatio n time status register (ostc). determine the oscillation stabilization time of the ostc regi ster and oscillation stabilization time select register (osts) after sufficientl y evaluating the oscillation stabiliz ation time with the resonator to be used. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 471 ring-osc oscillator characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 480 khz subsystem clock oscillator characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd oscillation frequency (f xt ) note 32 32.768 35 khz xt1 input frequency (f xt ) note 32 38.5 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 12 15 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designe d as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular care is therefore required with the wiring me thod when the subsystem clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 472 recommended oscillator constants caution for the resona tor selection of the ? ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 473 dc characteristics (1/4) (t a = ? ? ? ? ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 474 dc characteristics (2/4) (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 475 dc characteristics (3/4): flash memory version (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 13.8 25.2 ma f xp = 10 mhz v dd = 5.0 v 10% notes 3, 7 when a/d converter is operating note 9 14.6 27.2 ma when a/d converter is stopped 8 14.6 ma f xp = 8.38 mhz v dd = 5.0 v 10% notes 3, 8 when a/d converter is operating note 9 9 16.6 ma when a/d converter is stopped 4.5 7.8 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 5 mhz v dd = 3.0 v 10% note 3 when a/d converter is operating note 9 5.1 9 ma when peripheral functions are stopped 1.8 3.6 ma f xp = 10 mhz v dd = 5.0 v 10% note 7 when peripheral functions are operating 8.9 ma when peripheral functions are stopped 0.9 1.8 ma f xp = 8.38 mhz v dd = 5.0 v 10% note 8 when peripheral functions are operating 6 ma when peripheral functions are stopped 0.41 0.82 ma i dd2 x1 crystal oscillation halt mode f xp = 5 mhz v dd = 3.0 v 10% when peripheral functions are operating 2.3 ma v dd = 5.0 v 10% 0.48 1.92 ma i dd3 ring-osc operating mode note 4 v dd = 3.0 v 10% 0.37 1.48 ma v dd = 5.0 v 10% 120 240 a i dd4 32.768 khz crystal oscillation operating mode notes 4, 6 v dd = 3.0 v 10% 91 182 a v dd = 5.0 v 10% 20 40 a i dd5 32.768 khz crystal oscillation halt mode notes 4, 6 v dd = 3.0 v 10% 6 12 a poc: off, ring: off 0.1 30 a poc: off, ring: on 14 58 a poc: on note 5 , ring: off 3.5 35.5 a v dd = 5.0 v 10% poc: on note 5 , ring: on 17.5 63.5 a poc: off, ring: off 0.05 10 a poc: off, ring: on 7.5 25 a poc: on note 5 , ring: off 3.5 15.5 a supply current note 1 i dd6 stop mode v dd = 3.0 v 10% poc: on note 5 , ring: on 11 30.5 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operatio n current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. when x1 oscillator is stopped. 5. including when lvie (bit 4 of lvim) = 1 in the pd78f0134m1, 78f0134m2, 78f0138m1, 78f0138m2, 78f0134m1(a), 78f0134m2(a), 78f 0138m1(a), and 78f0138m2 (a). 6. when the pd78f0134m1, 78f0134m2, 78f0138m1, 78f0138m2, 78f 0134m1(a), 78f0134m2(a), 78f0138m1(a), and 78f0138m2(a) (including lvie = 0) are selected and ring-osc oscillation is stopped. 7. when the regc pin is directly connected to v dd . 8. when the regc pin is connected to v ss via a capacitor (1 f: recommended). 9. including the current that flows through the av ref pin. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 476 dc characteristics (4/4): mask rom version (t a = ? when the regc pin is connected to v ss via a capacitor (1 including the current that flows through the av ref pin. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 477 ac characteristics (1) basic operation (t a = ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 478 t cy vs. v dd (x1 input clock operation) (a) when regc pin is connected to v ss via capacitor (1 f: recommended) 5.0 1.0 2.0 0.4 0.2 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 guaranteed operation range 20.0 16.0 0.238 supply voltage v dd [v] cycle time t cy [ s] (b) when regc pin is connected directly to v dd 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 3.3 guaranteed operation range 20.0 16.0 0.238 chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 479 (2) serial interface (t a = ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 480 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 481 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0: chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 482 a/d converter characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.4 %fsr overall error notes 1, 2 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 4.0 v av ref 5.5 v 14 100 s conversion time t conv 2.7 v av ref < 4.0 v 17 100 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 483 poc circuit characteristics (t a = ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 484 lvi circuit characteristics (t a = ? ? chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 485 flash memory programming character istics: flash memory version (t a = +10 to +60 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xp = 10 mhz, v dd = 5.5 v 37 ma v pp supply current i pp v pp = v pp2 100 ma step erase time note 1 t er 0.199 0.2 0.201 s overall erase time note 2 t era when step erase time = 0.2 s 20 s/chip writeback time note 3 t wb 49.4 50 50.6 ms number of writebacks per 1 writeback command note 4 c wb when writeback time = 50 ms 60 times number of erases/writebacks c erwb 16 times step write time note 5 t wr 48 50 52 s overall write time per word note 6 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/ area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the is suance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark the range of the operating clock during flash memory programming is the same as the range during normal operation. chapter 29 electrical specifications (standard products, (a) grade products) user?s manual u16228ej2v0ud 486 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 10 s v pp pulse input start time from reset t rp 2 ms v pp pulse high-/low-level width t pw 8 s v pp pulse input end time from reset t rpe 14 ms v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe user?s manual u16228ej2v0ud 487 chapter 30 electrical specifi cations ((a1) grade products) target products: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 488 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 16 ma per pin p60 to p63 24 ma p00 to p06, p40 to p43, p50 to p53, p70 to p77 28 ma output current, low i ol total of all pins 56 ma p10 to p17, p30 to p33, p60 to p63, p120, p130, p140, p141 28 ma mask rom version ? 40 to +110 in normal operation mode ? 40 to +105 operating ambient temperature t a flash memory version in flash memory programming mode ? 40 to +85 c mask rom version ? 65 to +150 storage temperature t stg flash memory version ? 40 to +125 c notes 1. must be 6.5 v or lower. 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (3.3 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops raise v dd 10 s or more after v pp falls below the lower-limit value (3 .3 v) of the operating voltage range of v dd (see b in the figure below). 3.3 v v dd 0 v 0 v v pp 3.3 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 489 x1 oscillator characteristics (t a = ? 40 to +110 c note 1 , 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 ceramic resonator note 2 c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 3 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 crystal resonator note 2 c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 3 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 x1 input frequency (f xp ) note 3 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 46 500 4.0 v v dd < 4.5 v 56 500 external clock note 2 x2 x1 x1 input high-/low-level width (t xph , t xpl ) 3.3 v v dd < 4.0 v 96 500 ns notes 1. t a = ? 40 to +110 c: pd780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1), 780138(a1) t a = ? 40 to +105 c: pd78f0134(a1), 78f0138(a1) 2. connect the regc pin directly to v dd . 3. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check the oscillation stabilization time of the x1 input clock using th e oscillation stabilization time status register (ostc). determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evalua ting the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 490 ring-osc oscillator characteristics (t a = ? 40 to +110 c note , 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 490 khz note t a = ? 40 to +110 c: pd780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1), 780138(a1) t a = ? 40 to +105 c: pd78f0134(a1), 78f0138(a1) subsystem clock oscillator characteristics (t a = ? 40 to +110 c note 1 , 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd oscillation frequency (f xt ) note 2 32 32.768 35 khz xt1 input frequency (f xt ) note 2 32 38.5 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 12 15 s notes 1. t a = ? 40 to +110 c: pd780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1), 780138(a1) t a = ? 40 to +105 c: pd78f0134(a1), 78f0138(a1) 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designe d as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular care is therefore required with the wiring me thod when the subsystem clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 491 dc characteristics (1/6): flash memory version (t a = ? ? ? ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 492 dc characteristics (2/6): flash memory version (t a = ? 40 to +105 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit p10 to p17, p30 to p33, p120, p130, p140, p141 total i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v p00 to p06, p40 to p43, p50 to p53, p70 to p77 total i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 3.3 v v dd < 4.0 v v dd ? 0.5 v p10 to p17, p30 to p33, p60 to p63, p120, p130, p140, p141 total i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v p00 to p06, p40 to p43, p50 to p53, p70 to p77 total i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v v ol1 i ol = 400 a 3.3 v v dd < 4.0 v 0.4 v output voltage, low v ol2 p60 to p63 i ol = 12 ma 2.0 v v i = v dd p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p140, p141, reset 10 a i lih1 v i = av ref p20 to p27 10 a i lih2 v i = v dd x1, x2 note 1 , xt1, xt2 note 1 20 a input leakage current, high i lih3 v i = 12 v p62, p63 (n-ch open drain) 20 a i lil1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p140, p141, reset ? 10 a i lil2 x1, x2 note 1 , xt1, xt2 note 1 ? 20 a input leakage current, low i lil3 v i = 0 v p62, p63 (n-ch open drain) ? 10 note 2 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a pull-up resistor r l v i = 0 v 10 30 120 k ? v pp supply voltage v pp1 in normal operation mode 0 0.2v dd v notes 1. when the inverse level of x1 is input to x2 a nd the inverse level of xt1 is input to xt2. 2. if port 6 has been set to input mode when a read instructio n is executed to read from port 6, a low-level input leakage current of up to ? 55 a flows during only one cycle. at all other times, the maximum leakage current is ? 10 a. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 493 dc characteristics (3/6): flash memory version (t a = ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 494 dc characteristics (4/6): mask rom version (t a = ? ? ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 495 dc characteristics (5/6): mask rom version (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 496 dc characteristics (6/6): mask rom version (t a = ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 497 ac characteristics (1) basic operation (t a = ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 498 t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 3.3 4.5 guaranteed operation range 20.0 16.0 0.238 chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 499 (2) serial interface (t a = ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 500 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note pd780133(a1), 780134(a1), 78f0134(a1), 780136(a1 ), 780138(a1), and 78f0138(a1) only. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 501 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0: pd780131(a1), 780132(a1) n = 0, 1: pd780133(a1), 780134(a1), 78f0134(a1), 780136(a1), 780138(a1), 78f0138(a1) chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 502 a/d converter characteristics (t a = ? ? ? ? ? ? chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 503 lvi circuit characteristics (t a = ? 40 to +110 c note 1 ) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.52 v v lvi1 3.9 4.1 4.32 v v lvi2 3.7 3.9 4.12 v v lvi3 3.5 3.7 3.92 v detection voltage v lvi4 3.3 3.5 3.72 v response time note 2 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time note 3 t lwait0 0.5 2.0 ms operation stabilization wait time note 4 t lwait1 0.1 0.2 ms notes 1. t a = ? 40 to +110 c: pd780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1), 780138(a1) t a = ? 40 to +105 c: pd78f0134(a1), 78f0138(a1) 2. time required from voltage detection to interrupt output or internal reset output. 3. time required from setting lvie to 1 to reference voltage stabilization when poc-off is selected by mask option (when flash memory version pd78f0134m1(a1), 78f0134m2(a1 ), 78f0138m1(a1), or 78f0138m2(a1) is used). 4. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 2. v pocn < v lvim (n = 0 or 1, m = 0 to 4) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t wait0 t lw t ld t wait1 lvie 1 lvion 1 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +110 c note 1 ) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr when poc-off is selected by mask option note 2 2.0 5.5 v release signal set time t srel 0 s notes 1. t a = ? 40 to +110 c: pd780131(a1), 780132(a1), 780133(a1), 780134(a1), 780136(a1), 780138(a1) t a = ? 40 to +105 c: pd78f0134(a1), 78f0138(a1) 2. when flash memory version pd78f0134m1(a1), 78f0134m2(a1), 78f0138m1(a1), or 78f0138m2(a1) is used chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 504 flash memory programming character istics: flash memory version (t a = +10 to +60 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xp = 10 mhz, v dd = 5.5 v 37 ma v pp supply current i pp v pp = v pp2 100 ma step erase time note 1 t er 0.199 0.2 0.201 s overall erase time note 2 t era when step erase time = 0.2 s 20 s/chip writeback time note 3 t wb 49.4 50 50.6 ms number of writebacks per 1 writeback command note 4 c wb when writeback time = 50 ms 60 times number of erases/writebacks c erwb 16 times step write time note 5 t wr 48 50 52 s overall write time per word note 6 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/ area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the is suance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark the range of the operating clock during flash memory programming is the same as the range during normal operation. chapter 30 electrical specifications ((a1) grade products) user?s manual u16228ej2v0ud 505 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 10 s v pp pulse input start time from reset t rp 2 ms v pp pulse high-/low-level width t pw 8 s v pp pulse input end time from reset t rpe 14 ms v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe user?s manual u16228ej2v0ud 506 chapter 31 electrical specifi cations ((a2) grade products) target products: pd780131(a2), 780132(a2), 780133(a2), 780134(a2), 780136(a2), 780138(a2) caution be sure to connect the regc pi n of (a2) grade products directly to v dd . absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v ev dd ? 0.3 to +6.5 v regc ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v ev ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note v supply voltage av ss ? 0.3 to +0.3 v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p130, p140, p141, x1, x2, xt1, xt2, reset ? 0.3 to v dd + 0.3 note v n-ch open drain ? 0.3 to + 13 v input voltage v i2 p62, p63 on-chip pull-up resistor ? 0.3 to v dd + 0.3 note v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v per pin ? 7 ma p00 to p06, p40 to p43, p50 to p53, p70 to p77 ? 21 ma output current, high i oh total of all pins ? 42 ma p10 to p17, p30 to p33, p120, p130, p140, p141 ? 21 ma note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 507 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit p00 to p06, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p130, p140, p141 14 ma per pin p60 to p63 21 ma p00 to p06, p40 to p43, p50 to p53, p70 to p77 24.5 ma output current, low i ol total of all pins 49 ma p10 to p17, p30 to p33, p60 to p63, p120, p130, p140, p141 24.5 ma operating ambient temperature t a in normal operation mode ? 40 to +125 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 508 x1 oscillator characteristics (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd < 5.5 v 2.0 8.38 ceramic resonator note 2 c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 1 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.0 v v dd < 5.5 v 2.0 8.38 crystal resonator note 2 c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 1 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.0 v v dd < 5.5 v 2.0 8.38 x1 input frequency (f xp ) note 1 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.0 v v dd < 5.5 v 56 500 external clock note 2 x2 x1 x1 input high-/low- level width (t xph , t xpl ) 3.3 v v dd < 4.0 v 96 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. connect the regc pin directly to v dd . cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check the oscillation stabilization time of the x1 input clock using th e oscillation stabilization time status register (ostc). determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evalua ting the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 509 ring-osc oscillator characteristics (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 495 khz subsystem clock oscillator characteristics (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd oscillation frequency (f xt ) note 32 32.768 35 khz xt1 input frequency (f xt ) note 32 38.5 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 12 15 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designe d as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular care is therefore required with the wiring me thod when the subsystem clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 510 dc characteristics (1/3) (t a = ? ? ? ? ? ? chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 511 dc characteristics (2/3) (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 512 dc characteristics (3/3) (t a = ? chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 513 ac characteristics (1) basic operation (t a = ? chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 514 t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 3.3 guaranteed operation range 20.0 16.0 0.238 chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 515 (2) serial interface (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 261.9 kbps (b) uart mode (uart0, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 261.9 kbps (c) 3-wire serial i/o mode (master m ode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 240 ns sck1n cycle time t kcy1 3.3 v v dd < 4.0 v 400 ns sck1n high-/low-level width t kh1 , t kl1 t kcy1 /2 ? 10 ns si1n setup time (to sck1n ) t sik1 30 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 100 pf note 30 ns note c is the load capacitance of the sck1n and so1n output lines. (d) 3-wire serial i/o mode (slave mode , sck1n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 100 pf note 120 ns note c is the load capacitance of the so1n output line. remark n = 0: pd780131(a2), 780132(a2) n = 0, 1: pd780133(a2), 780134(a2), 780136(a2), 780138(a2) chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 516 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note pd780133(a2), 780134(a2), 780136(a2), and 780138(a2) only. chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 517 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0: pd780131(a2), 780132(a2) n = 0, 1: pd780133(a2), 780134(a2), 780136(a2), and 780138(a2) chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 518 a/d converter characteristics (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.7 %fsr overall error notes 1, 2 3.3 v av ref < 4.0 v 0.3 0.9 %fsr 4.0 v av ref 5.5 v 16 48 s conversion time t conv 3.3 v av ref < 4.0 v 19 48 s 4.0 v av ref 5.5 v 0.7 %fsr zero-scale error notes 1, 2 3.3 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 0.7 %fsr full-scale error notes 1, 2 3.3 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 5.5 lsb integral non-linearity error note 1 3.3 v av ref < 4.0 v 7.5 lsb 4.0 v av ref 5.5 v 2.5 lsb differential non-linearity error note 1 3.3 v av ref < 4.0 v 3.0 lsb analog input voltage v ian av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. poc circuit characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit detection voltage v poc0 mask option = 3.5 v 3.3 3.5 3.76 v power supply rise time t pth v dd : 0 v 3.3 v 0.002 ms response delay time 1 note t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note t pd when v dd falls 1.0 ms minimum pulse width t pw 0.2 ms note time required from voltage detection to reset release. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd chapter 31 electrical specifications ((a2) grade products) user?s manual u16228ej2v0ud 519 lvi circuit characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.56 v v lvi1 3.9 4.1 4.36 v v lvi2 3.7 3.9 4.16 v v lvi3 3.5 3.7 3.96 v detection voltage v lvi4 3.3 3.5 3.76 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time note 2 t lwait0 0.5 2.0 ms operation stabilization wait time note 3 t lwait1 0.1 0.2 ms notes 1. time required from voltage detection to interrupt output or internal reset output. 2. time required from setting lvie to 1 to reference vo ltage stabilization when poc-off is selected by the mask option. 3. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 2. v pocn < v lvim (n = 0 or 1, m = 0 to 4) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t wait0 t lw t ld t wait1 lvie 1 lvion 1 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr when poc-off is selected by mask option 2.0 5.5 v release signal set time t srel 0 s user?s manual u16228ej2v0ud 520 chapter 32 package drawings m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-2 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. chapter 32 package drawings user?s manual u16228ej2v0ud 521 64-pin plastic lqfp (14x14) note each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.2 14.0 0.2 0.8 (t.p.) 1.0 j 17.2 0.2 k c 14.0 0.2 i 0.20 1.6 0.2 l 0.8 f 1.0 n p q 0.10 1.4 0.1 0.127 0.075 u 0.886 0.15 r s 3 1.7 max. t 0.25 p64gc-80-8bs h 0.37 + 0.08 ? 0.07 m 0.17 + 0.03 ? 0.06 s n j t detail of lead end c d a b k m i s p r l u q g f m h + 4 ? 3 1 64 49 17 32 16 48 33 s chapter 32 package drawings user?s manual u16228ej2v0ud 522 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1 user?s manual u16228ej2v0ud 523 chapter 33 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 33-1. surface mounting type soldering cond itions (1/6) (1) mask rom version (gb-8eu type) 64-pin plastic lqfp (10 ? chapter 33 recommended soldering conditions user?s manual u16228ej2v0ud 524 table 33-1. surface mounting type soldering cond itions (2/6) (2) mask rom version (gc-8bs type) 64-pin plastic lqfp (14 ? chapter 33 recommended soldering conditions user?s manual u16228ej2v0ud 525 table 33-1. surface mounting type soldering cond itions (3/6) (3) mask rom version (gk-9et type) 64-pin plastic tqfp (12 ? chapter 33 recommended soldering conditions user?s manual u16228ej2v0ud 526 table 33-1. surface mounting type soldering cond itions (4/6) (4) flash memory version (gb-8eu type) 64-pin plastic lqfp (10 ? chapter 33 recommended soldering conditions user?s manual u16228ej2v0ud 527 table 33-1. surface mounting type soldering cond itions (5/6) (5) flash memory version (gc-8bs type) 64-pin plastic lqfp (14 ? chapter 33 recommended soldering conditions user?s manual u16228ej2v0ud 528 table 33-1. surface mounting type soldering cond itions (6/6) (6) flash memory version (gk-9et type) 64-pin plastic tqfp (12 ? user?s manual u16228ej2v0ud 529 chapter 34 cautions for wait 34.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruct ion increases by the number of wait clocks (for the number of wait clocks, refer to table 34-1 ). this must be noted when real-time processing is performed. chapter 34 cautions for wait user?s manual u16228ej2v0ud 530 34.2 peripheral hardware that generates wait table 34-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 34-1. registers that generate wait and number of cpu wait clocks peripheral hardware register a ccess number of wait clocks watchdog timer wdtm write 3 clocks (fixed) serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write pfm write pft write 2 to 5 clocks note (when adm.5 flag = ?1?) 2 to 9 clocks note (when adm.5 flag = ?0?) adcr read 1 to 5 clocks (when adm.5 flag = ?1?) 1 to 9 clocks (when adm.5 flag = ?0?) a/d converter chapter 34 cautions for wait user?s manual u16228ej2v0ud 531 34.3 example of wait occurrence <1> watchdog timer user?s manual u16228ej2v0ud 532 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0/ke1. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows unless otherwise specified, ?windows? means the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver 4.0 appendix a development tools user?s manual u16228ej2v0ud 533 figure a-1. development tool configuration (1/2) (1) when using the in-circuit em ulators ie-78k0-ns, ie-78k0-ns-a language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator note 3 emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory software package project manager (windows only) note 2 software package flash memory write environment control software embedded software real-time os performance board power supply unit notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. 3. products other than in-circuit emulators ie-78k0- ns and ie-78k0-ns-a are all sold separately. appendix a development tools user?s manual u16228ej2v0ud 534 figure a-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-78k0k1-et language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator note 3 emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory software package project manager (windows only) note 2 software package flash memory write environment control software embedded software real-time os power supply unit notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. 3. in-circuit emulator ie-78k0k1-et is supplied with integrated debugger id78k0-ns, a device file, power supply unit, and pci bus interface adapter ie-70000-pc i-if-a. any other products are sold separately. appendix a development tools user?s manual u16228ej2v0ud 535 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df780138) (sold separately). appendix a development tools user?s manual u16228ej2v0ud 536 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df780138 s cc78k0-l host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4) solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. appendix a development tools user?s manual u16228ej2v0ud 537 a.5 debugging tools (hardware) a.5.1 when using in-circuit emul ators ie-78k0-ns and ie-78k0-ns-a ie-78k0-ns in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k/0 series pr oduct. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-78k0-ns-pa performance board this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. ie-78k0-ns-a in-circuit emulator product that combines the ie-78k0-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a 100 v to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. ie-780148-ns-em1 emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. np-64gb-tq np-h64gb-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plasti c lqfp (gb-8eu type). tgb-064sdp conversion adapter this conversion adapter is used to conne ct the np-64gb-tq or np-h64gb-tq and target system board to which a 64-pin pl astic lqfp (gb-8eu type) can be connected. np-64gc-tq np-h64gc-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plastic lqfp (gc-8bs type). tgc-064sap conversion adapter this conversion adapter is used to conne ct the np-64gc-tq or np-h64gc-tq and target system board to which a 64-pin pl astic lqfp (gc-8bs type) can be connected. np-64gk np-h64gk-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plastic tqfp (gk-9et type). tgk-064sbw conversion adapter this conversion adapter is used to connect the np-64gk or np-h64gk-tq and target system board to which a 64-pin plasti c tqfp (gk-9et type) can be connected. remarks 1. np-64gb-tq, np-h64gb-tq, np-64gc-tq, np -h64gc-tq, np-64gk, and np-h64gk-tq are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgb-064sdp, tgc-064-sap, and tgk-064sbw are products made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) appendix a development tools user?s manual u16228ej2v0ud 538 a.5.2 when using in-circu it emulator ie-78k0k1-et ie-78k0k1-et notes 1, 2 in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k0/kx1 produc t. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. this is supplied with ie-78k0k1-et. np-64gb-tq np-h64gb-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plasti c lqfp (gb-8eu type). tgb-064sdp conversion adapter this conversion adapter is used to conne ct the np-64gb-tq or np-h64gb-tq and target system board to which a 64-pin pl astic lqfp (gb-8eu type) can be connected. np-64gc-tq np-h64gc-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plastic lqfp (gc-8bs type). tgc-064sap conversion adapter this conversion adapter is used to conne ct the np-64gc-tq or np-h64gc-tq and target system board to which a 64-pin pl astic lqfp (gc-8bs type) can be connected. np-64gk np-h64gk-tq emulation probe this emulation probe is used to connect the in-c ircuit emulator and target system, and is designed for a 64-pin plastic tqfp (gk-9et type). tgk-064sbw conversion adapter this conversion adapter is used to connect the np-64gk or np-h64gk-tq and target system board to which a 64-pin plasti c tqfp (gk-9et type) can be connected. notes 1. ie-78k0k1-et is supplied with a power supply unit and pci bus interface adapter ie-70000-pci-if-a. it is also supplied with integrated debugger id78k 0-ns and a device file as control software. 2. under development remarks 1. np-64gb-tq, np-h64gb-tq, np-64gc-tq, np -h64gc-tq, np-64gk, and np-h64gk-tq are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgb-064sdp, tgc-064-sap, and tgk-064sbw are products made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) appendix a development tools user?s manual u16228ej2v0ud 539 a.6 debugging tools (software) this is a system simulator for the 78k /0 series. the sm78k0 is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780138) (sold separately). sm78k0 system simulator part number: s sm78k0 this debugger supports the in-circuit emulator s for the 78k/0 series. the id78k0-ns is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (sold separately). id78k0-ns integrated debugger (supporting in-circuit emulators ie-78k0-ns, ie-78k0-ns-a, and ie-78k0k1-et) part number: s id78k0-ns remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom appendix a development tools user?s manual u16228ej2v0ud 540 a.7 embedded software the rx78k0 is a real-time os conforming to the itron specifications. a tool (configurator) for generating the nucleus of the rx78k0 and multiple information tables is supplied. used in combination with an assembler pac kage (ra78k0) and device file (df780138) (both sold separately). user?s manual u16228ej2v0ud 541 appendix b notes on target system design the following shows a diagram of t he connection conditions between the em ulation probe and conversion adapter. design your system making allowances for conditions such as the shape of parts mount ed on the target system, as shown below. table b-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-64gb-tq 155 mm np-h64gb-tq tgb-064sdp 355 mm np-64gc-tq 155 mm np-h64gc-tq tgc-064sap 355 mm np-64gk 155 mm np-h64gk-tq tgk-064sbw 355 mm figure b-1. distance between in-circu it emulator and conversion adapter 155 mm note in-circuit emulator ie-78k0-ns, ie-78k0-ns-a, or ie-78k0k1-et emulation board ie-780148-ns-em1 conversion adapter tgb-064sdp, tgc-064sap, tgk-064sbw target system cn1 78013x probe board emulation probe np-64gb-tq, np-h64gb-tq, np-64gc-tq, np-h64gc-tq, np-64gk, np-h64gk-tq note distance when using np-64gb-tq, np-64gc-tq, or np-64gk. th is is 355 mm when using np-h64gb- tq, np-h64gc-tq, or np-h64gk-tq. remark the np-64gb-tq, np-h64gb-tq, np-64gc-tq, np-h64gc-tq, np-64gk, and np-h64gk-tq are products of naito densei machida mfg. co., ltd. the tgb-064sdp, tgc-064sap, and tgk-064sbw are products of tokyo eletech corporation. appendix b notes on target system design user?s manual u16228ej2v0ud 542 figure b-2. connection conditions of ta rget system (when using np-64gb-tq) emulation probe np-64gb-tq emulation board ie-780148-ns-em1 22 mm 40 mm 34 mm target system conversion adapter tgb-064sdp 16 mm pin 1 11 mm 16 mm appendix b notes on target system design user?s manual u16228ej2v0ud 543 figure b-3. connection conditions of ta rget system (when using np-h64gb-tq) emulation probe np-h64gb-tq emulation board ie-780148-ns-em1 21.4 mm 42.6 mm 45 mm 16 mm target system conversion adapter tgb-064sdp 16 mm pin 1 11 mm appendix b notes on target system design user?s manual u16228ej2v0ud 544 figure b-4. connection conditions of ta rget system (when using np-64gc-tq) emulation probe np-64gc-tq emulation board ie-780148-ns-em1 23 mm 25 mm 40 mm 34 mm target system conversion adapter tgc-064sap 20.65 mm pin 1 11 mm 20.65 mm appendix b notes on target system design user?s manual u16228ej2v0ud 545 figure b-5. connection conditions of ta rget system (when using np-h64gc-tq) emulation probe np-h64gc-tq emulation board ie-780148-ns-em1 23 mm 23 mm 42 mm 45 mm target system conversion adapter: tgc-064sap 20.65 mm pin 1 11 mm 20.65 mm appendix b notes on target system design user?s manual u16228ej2v0ud 546 figure b-6. connection conditions of target system (when using np-64gk) emulation probe np-64gk emulation board ie-780148-ns-em1 21.95 mm 40 mm 34 mm target system conversion adapter tgk-064sbw 18.4 mm pin 1 11 mm 25 mm 18.4 mm appendix b notes on target system design user?s manual u16228ej2v0ud 547 figure b-7. connection conditions of ta rget system (when using np-h64gk-tq) emulation probe np-h64gk-tq emulation board ie-780148-ns-em1 42 mm 45 mm 18.4 mm 11 mm target system conversion adapter tgk-064sbw 18.4 mm pin 1 21.95 mm 23 mm user?s manual u16228ej2v0ud 548 appendix c register index c.1 register index (in alphabetical or der with respect to register names) [a] a/d conversion resu lt regist er (a dcr).......................................................................................... ..............................257 a/d converter mode register (adm) .............................................................................................. ..............................254 analog input channel specification re gister (ads) .............................................................................. ........................256 asynchronous serial interface control register 6 (asi cl6) ...................................................................... ....................306 asynchronous serial interface operat ion mode regist er 0 (a sim0) ................................................................ .............276 asynchronous serial interface operat ion mode regist er 6 (a sim6) ................................................................ .............300 asynchronous serial interface recepti on error status regi ster 0 ( asis0) ........................................................ .............278 asynchronous serial interface recepti on error status regi ster 6 ( asis6) ........................................................ .............302 asynchronous serial interface transmi ssion status regi ster 6 ( asif6) ........................................................... .............303 [b] baud rate generator contro l register 0 (brg c0) ................................................................................. ........................279 baud rate generator contro l register 6 (brg c6) ................................................................................. ........................305 [c] capture/compare contro l register 00 (crc0 0).................................................................................... ........................153 capture/compare contro l register 01 (crc0 1).................................................................................... ........................154 clock monitor mode re gister (clm) .............................................................................................. ..............................402 clock output selectio n register (cks) .......................................................................................... ...............................248 clock selection regi ster 6 (c ksr6)............................................................................................. ................................304 correction address r egister 0 (corad 0)......................................................................................... ...........................427 correction address r egister 1 (corad 1)......................................................................................... ...........................427 correction control register (corcn) ............................................................................................ ..............................428 [e] 8-bit timer compare re gister 50 (cr50) ......................................................................................... ..............................190 8-bit timer compare re gister 51 (cr51) ......................................................................................... ..............................190 8-bit timer coun ter 50 (t m50).................................................................................................. ....................................189 8-bit timer coun ter 51 (t m51).................................................................................................. ....................................189 8-bit timer h carrier cont rol register 1 (tmc yc1).............................................................................. ..........................213 8-bit timer h compare register 00 (cmp00)...................................................................................... ...........................208 8-bit timer h compare register 01 (cmp01)...................................................................................... ...........................208 8-bit timer h compare register 10 (cmp10)...................................................................................... ...........................208 8-bit timer h compare register 11 (cmp11)...................................................................................... ...........................208 8-bit timer h mode re gister 0 (tmhmd0) ......................................................................................... ...........................209 8-bit timer h mode re gister 1 (tmhmd1) ......................................................................................... ...........................209 8-bit timer mode contro l register 50 (tmc 50)................................................................................... ...........................193 8-bit timer mode contro l register 51 (tmc 51)................................................................................... ...........................194 external interrupt falling edg e enable regist er (egn).......................................................................... ........................369 external interrupt rising e dge enable regist er (egp)........................................................................... ........................369 appendix c register index user?s manual u16228ej2v0ud 549 [i] input switch contro l register (isc) ............................................................................................ ...................................307 internal expansion ram size switching regi ster (ixs)........................................................................... ......................438 internal memory size s witching regist er (ims) .................................................................................. ..........................437 interrupt mask flag re gister 0h (mk0h) ......................................................................................... .............................367 interrupt mask flag re gister 0l (mk0l)......................................................................................... ...............................367 interrupt mask flag re gister 1h (mk1h) ......................................................................................... .............................367 interrupt mask flag re gister 1l (mk1l)......................................................................................... ...............................367 interrupt request flag register 0h (if0h) ...................................................................................... ...............................366 interrupt request flag register 0l (if 0l) ...................................................................................... ................................366 interrupt request flag register 1h (if1h) ...................................................................................... ...............................366 interrupt request flag register 1l (if 1l) ...................................................................................... ................................366 [k] key return mode re gister (krm) ................................................................................................. ................................379 [l] low-voltage detection level selection regi ster (l vis).......................................................................... ........................415 low-voltage detecti on register (lvim) .......................................................................................... ..............................414 [m] main clock mode register (mcm) ................................................................................................. ...............................122 main osc control register (moc) ................................................................................................ ...............................123 multiplication/division data r egister a0 (md a0h, md a0l) ........................................................................ ..................353 multiplication/division dat a register b0 (mdb0)................................................................................ ...........................354 multiplier/divider contro l register 0 (dm uc0) .................................................................................. ............................355 [o] oscillation stabilization time c ounter status r egister (ostc) .................................................................. ............124, 382 oscillation stabilization time select regi ster (osts).......................................................................... ..................125, 383 [p] port mode regist er 0 (p m0)..................................................................................................... .................... 112, 15 9, 339 port mode regist er 1 (p m1)................................................................................................. 112, 195, 213, 280, 307, 339 port mode regist er 12 (p m12)................................................................................................... ..................................112 port mode regist er 14 (p m14)................................................................................................... ..........................112, 250 port mode regist er 3 (p m3)..................................................................................................... ............................112, 195 port mode regist er 4 (p m4)..................................................................................................... ....................................112 port mode regist er 5 (p m5)..................................................................................................... ....................................112 port mode regist er 6 (p m6)..................................................................................................... ....................................112 port mode regist er 7 (p m7)..................................................................................................... ....................................112 port regist er 0 (p0)........................................................................................................... ...........................................114 port regist er 1 (p1)........................................................................................................... ...........................................114 port register 12 (p12) ......................................................................................................... .........................................114 port register 13 (p13) ......................................................................................................... .........................................114 port register 14 (p14) ......................................................................................................... .........................................114 port regist er 2 (p2)........................................................................................................... ...........................................114 port regist er 3 (p3)........................................................................................................... ...........................................114 appendix c register index user?s manual u16228ej2v0ud 550 port regist er 4 (p4)........................................................................................................... ...........................................114 port regist er 5 (p5)........................................................................................................... ...........................................114 port regist er 6 (p6)........................................................................................................... ...........................................114 port regist er 7 (p7)........................................................................................................... ...........................................114 power-fail comparison mo de register (pfm) ...................................................................................... .........................258 power-fail comparison th reshold regi ster (pft) ................................................................................. .........................258 prescaler mode regi ster 00 (prm00)............................................................................................. .............................157 prescaler mode regi ster 01 (prm01)............................................................................................. .............................157 priority specification fl ag register 0h (p r0h) ................................................................................. .............................368 priority specification fl ag register 0l (p r0l) ................................................................................. ..............................368 priority specification fl ag register 1h (p r1h) ................................................................................. .............................368 priority specification fl ag register 1l (p r1l) ................................................................................. ..............................368 processor clock cont rol regist er (pcc) ......................................................................................... ..............................119 pull-up resistor opti on register 0 (pu0) ....................................................................................... ................................115 pull-up resistor opti on register 1 (pu1) ....................................................................................... ................................115 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ..............................115 pull-up resistor opti on register 14 (pu 14) ..................................................................................... ..............................115 pull-up resistor opti on register 3 (pu3) ....................................................................................... ................................115 pull-up resistor opti on register 4 (pu4) ....................................................................................... ................................115 pull-up resistor opti on register 5 (pu5) ....................................................................................... ................................115 pull-up resistor opti on register 7 (pu7) ....................................................................................... ................................115 [r] receive buffer regi ster 0 (rxb0) ............................................................................................... .................................275 receive buffer regi ster 6 (rxb6) ............................................................................................... .................................299 remainder data regi ster 0 (sdr0)............................................................................................... ...............................353 reset control flag register (resf) ............................................................................................. .................................400 ring-osc mode r egister (rcm) ................................................................................................... ..............................121 [s] serial clock selection register 10 (csic10) .................................................................................... .............................336 serial clock selection register 11 (csic11) .................................................................................... .............................336 serial i/o shift regi ster 10 (sio10) ........................................................................................... ...................................333 serial i/o shift regi ster 11 (sio11) ........................................................................................... ...................................333 serial operation mode register 10 (csim 10) ..................................................................................... ..........................334 serial operation mode register 11 (csim 11) ..................................................................................... ..........................334 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ......................147 16-bit timer capture/compar e register 001 (c r001) .............................................................................. ......................147 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ......................149 16-bit timer capture/compar e register 011 (c r011) .............................................................................. ......................149 16-bit timer count er 00 (t m00)................................................................................................. ...................................147 16-bit timer count er 01 (t m01)................................................................................................. ...................................147 16-bit timer mode contro l register 00 (tmc 00).................................................................................. ..........................150 16-bit timer mode contro l register 01 (tmc 01).................................................................................. ..........................150 16-bit timer output cont rol register 00 (t oc00)................................................................................ ...........................154 16-bit timer output cont rol register 01 (t oc01)................................................................................ ...........................154 appendix c register index user?s manual u16228ej2v0ud 551 [t] timer clock selection register 50 (tcl50) ...................................................................................... ............................191 timer clock selection register 51 (tcl51) ...................................................................................... ............................191 transmit buffer regi ster 10 (s otb10)........................................................................................... ..............................333 transmit buffer regi ster 11 (s otb11)........................................................................................... ..............................333 transmit buffer regi ster 6 (txb6).............................................................................................. ..................................299 transmit shift regi ster 0 (txs0) ............................................................................................... ...................................275 [w] watch timer operation mode register (wtm) ...................................................................................... ........................232 watchdog timer enable register (wdte) .......................................................................................... ..........................241 watchdog timer mode r egister (wdtm) ............................................................................................ .........................240 appendix c register index user?s manual u16228ej2v0ud 552 c.2 register index (in al phabetical order with respect to register symbol) [a] adcr: a/d conversion result regist er ........................................................................................... ......................257 adm: a/d converte r mode re gister............................................................................................... .....................254 ads: analog input channel specific ation re gister ............................................................................... ..............256 asicl6: asynchronous serial in terface control register 6....................................................................... ...............306 asif6: asynchronous serial interface transmission status register 6 ............................................................ ......303 asim0: asynchronous serial interf ace operation mode register 0................................................................. .......276 asim6: asynchronous serial interf ace operation mode register 6................................................................. .......300 asis0: asynchronous serial interface re ception error stat us regist er 0......................................................... ......278 asis6: asynchronous serial interface re ception error stat us regist er 6......................................................... ......302 [b] brgc0: baud rate generato r control r egister 0 .................................................................................. ...................279 brgc6: baud rate generato r control r egister 6 .................................................................................. ...................305 [c] cks: clock output se lection re gister ........................................................................................... .....................248 cksr6: clock select ion register 6 .............................................................................................. ..........................304 clm: clock monito r mode re gister............................................................................................... .....................402 cmp00: 8-bit timer h compare regi ster 00 ....................................................................................... .....................208 cmp01: 8-bit timer h compare regi ster 01 ....................................................................................... .....................208 cmp10: 8-bit timer h compare regi ster 10 ....................................................................................... .....................208 cmp11: 8-bit timer h compare regi ster 11 ....................................................................................... .....................208 corad0: correction a ddress regi ster 0 .......................................................................................... ........................427 corad1: correction a ddress regi ster 1 .......................................................................................... ........................427 corcn: correction c ontrol r egister ............................................................................................. ..........................428 cr000: 16-bit timer capture/ compare regi ster 000............................................................................... ................147 cr001: 16-bit timer capture/ compare regi ster 001............................................................................... ................147 cr010: 16-bit timer capture/ compare regi ster 010............................................................................... ................149 cr011: 16-bit timer capture/ compare regi ster 011............................................................................... ................149 cr50: 8-bit timer co mpare regi ster 50.......................................................................................... ......................190 cr51: 8-bit timer co mpare regi ster 51.......................................................................................... ......................190 crc00: capture/compare control regi ster 00 ..................................................................................... ..................153 crc01: capture/compare control regi ster 01 ..................................................................................... ..................154 csic10: serial clock se lection regi ster 10 ..................................................................................... ........................336 csic11: serial clock se lection regi ster 11 ..................................................................................... ........................336 csim10: serial operat ion mode regi ster 10...................................................................................... ......................334 csim11: serial operat ion mode regi ster 11...................................................................................... ......................334 [d] dmuc0: multiplier/divider control re gister 0 ................................................................................... ........................355 [e] egn: external interrupt falling edge enabl e regi ster ........................................................................... ..............369 egp: external interrupt rising edge enabl e regi ster ............................................................................ ..............369 appendix c register index user?s manual u16228ej2v0ud 553 [i] if0h: interrupt reques t flag regi ster 0h....................................................................................... ......................366 if0l: interrupt reques t flag regi ster 0l ....................................................................................... ......................366 if1h: interrupt reques t flag regi ster 1h....................................................................................... ......................366 if1l: interrupt reques t flag regi ster 1l ....................................................................................... ......................366 ims: internal memory si ze switchin g regi ster ................................................................................... ...............437 isc: input switch control r egist er............................................................................................. ........................307 ixs: internal expansion ram size switchin g regi ster ............................................................................ ..........438 [k] krm: key return mode re gister.................................................................................................. .......................379 [l] lvim: low-voltage de tection re gister ........................................................................................... .....................414 lvis: low-voltage detection level selecti on regi ster ........................................................................... ..............415 [m] mcm: main clo ck mode re gister .................................................................................................. ......................122 mda0h: multiplication/div ision data r egister a0 ................................................................................ ....................353 mda0l: multiplication/div ision data r egister a0 ................................................................................ ....................353 mdb0: multiplication/div ision data r egister b0 ................................................................................. ...................354 mk0h: interrupt mask flag regist er 0h .......................................................................................... ......................367 mk0l: interrupt mask flag regist er 0l.......................................................................................... .......................367 mk1h: interrupt mask flag regist er 1h .......................................................................................... ......................367 mk1l: interrupt mask flag regist er 1l.......................................................................................... .......................367 moc: main osc c ontrol r egister ................................................................................................. ......................123 [o] ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... .....124, 382 osts: oscillation stabilizati on time select register ........................................................................... ..........125, 383 [p] p0: port r egister 0............................................................................................................ ..............................114 p1: port r egister 1............................................................................................................ ..............................114 p12: port r egister 12.......................................................................................................... ..............................114 p13: port r egister 13.......................................................................................................... ..............................114 p14: port r egister 14.......................................................................................................... ..............................114 p2: port r egister 2............................................................................................................ ..............................114 p3: port r egister 3............................................................................................................ ..............................114 p4: port r egister 4............................................................................................................ ..............................114 p5: port r egister 5............................................................................................................ ..............................114 p6: port r egister 6............................................................................................................ ..............................114 p7: port r egister 7............................................................................................................ ..............................114 pcc: processor cloc k control register .......................................................................................... ....................119 pfm: power-fail compar ison mode regist er ....................................................................................... ...............258 pft: power-fail comparis on threshol d regi ster .................................................................................. ..............258 pm0: port mode register 0...................................................................................................... .......... 112, 159, 339 pm1: port mode regist er 1........................................................................................ 112, 195, 213, 280, 307, 339 appendix c register index user?s manual u16228ej2v0ud 554 pm12: port mode register 12 .................................................................................................... ..........................112 pm14: port mode register 14 .................................................................................................... ..................112, 250 pm3: port mode register 3 ...................................................................................................... ..................112, 195 pm4: port mode register 4 ...................................................................................................... ..........................112 pm5: port mode register 5 ...................................................................................................... ..........................112 pm6: port mode register 6 ...................................................................................................... ..........................112 pm7: port mode register 7 ...................................................................................................... ..........................112 pr0h: priority specificat ion flag r egister 0h .................................................................................. .....................368 pr0l: priority specificat ion flag r egister 0l .................................................................................. ......................368 pr1h: priority specificat ion flag r egister 1h .................................................................................. .....................368 pr1l: priority specificat ion flag r egister 1l .................................................................................. ......................368 prm00: prescaler m ode register 00 .............................................................................................. .......................157 prm01: prescaler m ode register 01 .............................................................................................. .......................157 pu0: pull-up resistor option regi ster 0 ........................................................................................ ......................115 pu1: pull-up resistor option regi ster 1 ........................................................................................ ......................115 pu12: pull-up resistor option regi ster 12 ...................................................................................... ......................115 pu14: pull-up resistor option regi ster 14 ...................................................................................... ......................115 pu3: pull-up resistor option regi ster 3 ........................................................................................ ......................115 pu4: pull-up resistor option regi ster 4 ........................................................................................ ......................115 pu5: pull-up resistor option regi ster 5 ........................................................................................ ......................115 pu7: pull-up resistor option regi ster 7 ........................................................................................ ......................115 [r] rcm: ring-osc m ode register .................................................................................................... .....................121 resf: reset contro l flag re gister.............................................................................................. ..........................400 rxb0: receive buffe r regist er 0 ................................................................................................ .........................275 rxb6: receive buffe r regist er 6 ................................................................................................ .........................299 [s] sdr0: remainder dat a regist er 0 ................................................................................................ .......................353 sio10: serial i/o sh ift register 10 ............................................................................................ ............................333 sio11: serial i/o sh ift register 11 ............................................................................................ ............................333 sotb10: transmit bu ffer regist er 10 ............................................................................................ ..........................333 sotb11: transmit bu ffer regist er 11 ............................................................................................ ..........................333 [t] tcl50: timer clock sele ction regi ster 50 ....................................................................................... ......................191 tcl51: timer clock sele ction regi ster 51 ....................................................................................... ......................191 tm00: 16-bit time r counter 00.................................................................................................. ...........................147 tm01: 16-bit time r counter 01.................................................................................................. ...........................147 tm50: 8-bit time r counte r 50................................................................................................... ............................189 tm51: 8-bit time r counte r 51................................................................................................... ............................189 tmc00: 16-bit timer mode control regi ster 00 ................................................................................... ....................150 tmc01: 16-bit timer mode control regi ster 01 ................................................................................... ....................150 tmc50: 8-bit timer mode control re gister 50 .................................................................................... .....................193 tmc51: 8-bit timer mode control re gister 51 .................................................................................... .....................194 tmcyc1: 8-bit timer h carri er control r egister 1 ............................................................................... .......................213 appendix c register index user?s manual u16228ej2v0ud 555 tmhmd0: 8-bit timer h mode regi ster 0.......................................................................................... .........................209 tmhmd1: 8-bit timer h mode regi ster 1.......................................................................................... .........................209 toc00: 16-bit timer output control re gister 00................................................................................. .....................154 toc01: 16-bit timer output control re gister 01................................................................................. .....................154 txb6: transmit buffe r register 6 ............................................................................................... .........................299 txs0: transmit shi ft register 0................................................................................................ ...........................275 [w] wdte: watchdog timer enable re gister ........................................................................................... ...................241 wdtm: watchdog time r mode r egist er ............................................................................................. ...................240 wtm: watch timer oper ation mode regist er ....................................................................................... ...............232 user?s manual u16228ej2v0ud 556 appendix d revision history d.1 major revisions in this edition (1/3) page description addition of products ? ? ? ? ? appendix d revision history user?s manual u16228ej2v0ud 557 (2/3) page description p. 133 modification of notes 4 and 5 in figure 5-13 status transition diagram (2) p. 135 modification of note 4 and illustration in figure 5-13 status transition diagram (4) p. 136 modification of table 5-3 relationship between operation clocks in each operation status p. 139 modification of note in figure 5-14 switching from ring-osc clock to x1 input clock (flowchart) p. 141 addition of note to figure 5-16 switching from x1 input clock to subsystem clock (flowchart) p. 144 revision of chapter 6 16-bit timer/event counters 00 and 01 p. 187 revision of chapter 7 8-bit timer/event counters 50 and 51 p. 205 revision of chapter 8 8-bit timers h0 and h1 p. 230 modification of figure 9-1 block diagram of watch timer p. 236 addition of figure 9-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) p. 247 modification of figure 11-1 block diagram of clock output/buzzer output controller p. 251 revision of chapter 12 a/d converter p. 272 revision of chapter 13 serial interface uart0 p. 293 revision of chapter 14 serial interface uart6 p. 331 revision of chapter 15 serial interfaces csi10 and csi11 p. 351 revision of chapter 16 multiplier/divider pp. 361, 362 addition of note to intvli, poc, and lvi in table 17-1 interrupt source list p. 365 addition of note 2 to table 17-2 flags corresponding to interrupt request sources p. 366 addition of caution 2 to figure 17-2 format of interrupt request flag registers (if0l, if0h, if1l, if1h) p. 369 addition of caution to table 17-3 ports corresponding to egpn and egnn p. 374 addition of software interrupt request item to table 17-5 relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing p. 378 modification of figure 18-1 block diagram of key interrupt p. 380 modification of table 19-1 relationship between halt mode, stop mode, and clock in old edition to table 19-1 relationship between operation clocks in each operation status p. 384 addition of cautions 2 and 3 to figure 19-1 format of oscillation stabilization time counter status register (ostc) p. 385 modification of table 19-2 operating statuses in halt mode p. 388 addition of (3) when subsystem clock is used as cpu clock to figure 19-4 halt mode release by reset input p. 389 modification of the following items in table 19-4 operating statuses in stop mode ? ? appendix d revision history user?s manual u16228ej2v0ud 558 (3/3) page description p. 408 addition of note to description in 22.1 functions of power-on-clear circuit p. 409 modification of figure 22-1 block diagram of power-on-clear circuit p. 412 addition of note to description in 23.1 functions of low-voltage detector p. 412 modification of figure 23-1 block diagram of low-voltage detector p. 414 modification of note 5 in figure 23-2 format of low-voltage detection register (lvim) p. 415 addition of note 2 and caution to figure 23-3 format of low-voltage detection level selection register (lvis) pp. 417, 419 modification of figure 23-4 timing of low-voltage detector internal reset signal generation and figure 23-5 timing of low-voltage detector interrupt signal generation p. 422 partial modification of description of (2) when used as interrupt under |
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